Script/Exp_Script/ChatGPT/Input/chatgpt_next_output_cleaned.csv

GCC,nvptx,0,
GCC,nvptx,1,"fprintf ( out , <STR_LIT> ) ;"
GCC,nvptx,2,else {
GCC,nvptx,3,
GCC,nvptx,4,
GCC,nvptx,5,stmt->tokens = tokens ;
GCC,nvptx,6,fork_wait();
GCC,nvptx,7,"obstack_ptr_grow(& argv_obstack, outlocation);"
GCC,nvptx,8,
GCC,nvptx,9,}
GCC,nvptx,10,
GCC,nvptx,11,
GCC,nvptx,12,
GCC,nvptx,13,"fprintf ( out , %d %d\n, nvars, nfuncs ) ;"
GCC,nvptx,14,"fprintf(out, Number of variables: %d, Number of functions: %d, nvars, nfuncs);"
GCC,nvptx,15,
GCC,nvptx,16,next = stmt -> next ;
GCC,nvptx,17,
GCC,nvptx,18,
GCC,nvptx,19,<debug> tool_cleanup( false );
GCC,nvptx,20,
GCC,nvptx,21,}
GCC,nvptx,22,c = bs + l ;
GCC,nvptx,23,break;
GCC,nvptx,24,
GCC,nvptx,25,"if ( fopenmp == true ) printf ( <STR_LIT> , get_version ( ) ) ;"
GCC,nvptx,26,
GCC,nvptx,27,
GCC,nvptx,28,
GCC,nvptx,29,
GCC,nvptx,30,unlink ( file );
GCC,nvptx,31,
GCC,nvptx,32,
GCC,nvptx,33,"for ( comma = , id = func_ids;"
GCC,nvptx,34,"buffer = XRESIZE ( buffer , char , alloc ) ;"
GCC,nvptx,35,base += n;
GCC,nvptx,36,
GCC,nvptx,37,with  }
GCC,nvptx,38,else {
GCC,nvptx,39,
GCC,nvptx,40,
GCC,nvptx,41,
GCC,nvptx,42,if ( GET_MODE_SIZE ( mode ) > UNITS_PER_WORD && split != BLKmode ) {
GCC,nvptx,43,if (cfun->machine->red_partition && regno_reg_rtx[i] != const0_rtx && split_mode_p(mode)) {
GCC,nvptx,44,
GCC,nvptx,45,
GCC,nvptx,46,}
GCC,nvptx,47,
GCC,nvptx,48,
GCC,nvptx,49,"diagnose_openacc_conflict ( TARGET_UNIFORM_GANG , <STR_LIT> ) ;"
GCC,nvptx,50,If (replaced_dots) XDELETE (replaced_dots) ;
GCC,nvptx,51,s << ptr_type_node ;
GCC,nvptx,52,'}
GCC,nvptx,53,
GCC,nvptx,54,if (TREE_CODE (type) != ARRAY_TYPE) {
GCC,nvptx,55,
GCC,nvptx,56,return ADDR_SPACE_GLOBAL;
GCC,nvptx,57,an else statement to handle the case where the condition is not met. For example: else {
GCC,nvptx,58,"fprintf ( file, <STR_LIT>, DECL_SIZE( TREE_TYPE (exp) ) / BITS_PER_UNIT,DECL_ALIGN( TREE_TYPE (exp) ) / BITS_PER_UNIT * BITS_PER_UNIT);"
GCC,nvptx,59,
GCC,nvptx,60,}
GCC,nvptx,61,switch ( GET_MODE ( op ) ) {
GCC,nvptx,62,
GCC,nvptx,63,chunk_offset++;
GCC,nvptx,64,
GCC,nvptx,65,}
GCC,nvptx,66,}
GCC,nvptx,67,
GCC,nvptx,68,}
GCC,nvptx,69,
GCC,nvptx,70,
GCC,nvptx,71,fclose(asm_out_file);
GCC,nvptx,72,"fprintf ( asm_out_file , <STR_LIT> , GET_VALUE_AT_ADDRESS ( Paddr ) ) ;"
GCC,nvptx,73,
GCC,nvptx,74,"else return gen_rtx_REG ( mode , 0 ) ;"
GCC,nvptx,75,if ( mode == TImode ) cum->count += <NUM_LIT> ;
GCC,nvptx,76,return BITS_PER_UNIT * <NUM_LIT> / 2;
GCC,nvptx,77,
GCC,nvptx,78,"return a specific value: a generated rtx UNSPEC value in the desired mode, with the number of arguments specified and an unspecified argument register."
GCC,nvptx,79,"return gen_rtx_CALL ( function_value_mode ( type ) , CALL_INSN_FUNCTION, gen_rtx_MEM ( Pmode, nvptx_ FUNCTION, gen_rtx_HIGH ( function_value_mode ( type ) , GEN_INT ( <NUM_LIT> ) ) ) , outgoing ? gen_rtx_CONST_INT ( Pmode, <NUM_LIT> ) : const0_rtx )"
GCC,nvptx,80,
GCC,nvptx,81,
GCC,nvptx,82,}
GCC,nvptx,83,return mode == cfun -> machine -> ret_reg_mode ;
GCC,nvptx,84,p->stack_frame_size = 0 ;
GCC,nvptx,85,
GCC,nvptx,86,if (code == UNSPEC_FROM_GLOBAL) return UNSPEC_FROM_GLOBAL;
GCC,nvptx,87,"rtx new_op = gen_rtx_ADDR_SPACE ( as , op ) ;"
GCC,nvptx,88,
GCC,nvptx,89,
GCC,nvptx,90,
GCC,nvptx,91,s> return mode;
GCC,nvptx,92,while (size --> NUM_LIST) {
GCC,nvptx,93,
GCC,nvptx,94,"case PRE_DEC: off = XEXP ( x , <NUM_LIT> ) ;"
GCC,nvptx,95,"case SYMBOL_REF : case LABEL_REF : output_addr_const ( file , x ) ;"
GCC,nvptx,96,"fprintf ( file , <STR_LIT> ) ;"
GCC,nvptx,97,return 0;
GCC,nvptx,98,}
GCC,nvptx,99,'switch (mode) {
GCC,nvptx,100,return <STR_LIT> ;
GCC,nvptx,101,if (force) {
GCC,nvptx,102,"decls_htab -> insert_to_hashtable ( name , decl ) ;"
GCC,nvptx,103,
GCC,nvptx,104,
GCC,nvptx,105,"fprintf ( asm_out_file , <STR_LIT> , (TREE_CODE ( decl ) == VAR_DECL ? <STR_LIT> : <STR_LIT>) , IDENTIFIER_POINTER ( DECL_ASSEMBLER_NAME ( decl ) ) ) ;"
GCC,nvptx,106,
GCC,nvptx,107,
GCC,nvptx,108,
GCC,nvptx,109,
GCC,nvptx,110,else {
GCC,nvptx,111,
GCC,nvptx,112,
GCC,nvptx,113,return <STR_LIT> ;
GCC,nvptx,114,
GCC,nvptx,115,if ( ! test ) {
GCC,nvptx,116,
GCC,nvptx,117,
GCC,nvptx,118,
GCC,nvptx,119,mode = arg_promotion ( Pmode ) ;
GCC,nvptx,120,
GCC,nvptx,121,{
GCC,nvptx,122,
GCC,nvptx,123,s << IR_TREE_PUBLIC ( decl ) << <STR_LIT>;
GCC,nvptx,124,s << void << name << (){
GCC,nvptx,125,"s << nvptx_ptx_type_from_mode ( mode , false ) ;"
GCC,nvptx,126,
GCC,nvptx,127,return arg_promotion ( mode ) ;
GCC,nvptx,128,if ( not equal arg types and type is not aggregate ) {
GCC,nvptx,129,
GCC,nvptx,130,": fwrite(file, &init_frag, sizeof(frag_t));"
GCC,nvptx,131,"fprintf (file, [%s]\n , name) ;"
GCC,nvptx,132,
GCC,nvptx,133,"printf(The size of the tree is %d, tree size);"
GCC,nvptx,134,
GCC,nvptx,135,"fprintf(file, The function's prototype has been written to the stringstream.);"
GCC,nvptx,136,}
GCC,nvptx,137,}
GCC,nvptx,138,
GCC,nvptx,139,
GCC,nvptx,140,
GCC,nvptx,141,
GCC,nvptx,142,"return nvptx_set_result_decl ( exp , target , result_decl ) ;"
GCC,nvptx,143,"emit_move_insn (varargs, stack_pointer_rtx);"
GCC,nvptx,144,
GCC,nvptx,145,
GCC,nvptx,146,
GCC,nvptx,147,}
GCC,nvptx,148,
GCC,nvptx,149,{
GCC,nvptx,150,cum->count--;
GCC,nvptx,151,
GCC,nvptx,152,"return nvptx_libcall_value ( mode , NULL_RTX ) ;"
GCC,nvptx,153,}
GCC,nvptx,154,return dest ;
GCC,nvptx,155,}
GCC,nvptx,156,break ;
GCC,nvptx,157,
GCC,nvptx,158,"gen_rtx_CLOBBER (<NUM_LIT>, DATA_SET_PTR (data , res)) ;"
GCC,nvptx,159,"tree addr = build2 ( ADDR_EXPR , type , fndecl , offset , size , align ) ;"
GCC,nvptx,160,
GCC,nvptx,161,
GCC,nvptx,162,
GCC,nvptx,163,
GCC,nvptx,164,
GCC,nvptx,165,
GCC,nvptx,166,
GCC,nvptx,167,}
GCC,nvptx,168,}
GCC,nvptx,169,
GCC,nvptx,170,"DEF ( GET_ADDR , <STR_LIT> , ( PTRVOID , ST , UINT , UINT , NULL_TREE ) ) ;"
GCC,nvptx,171,
GCC,nvptx,172,"<c> if ( ! cfun -> machine -> doing_call ) return gen_rtx_REG ( mode , NVPTX_RETURN_REGNUM ) ;"
GCC,nvptx,173,tree acc_out = make_ssa_name ( var_type ) ;
GCC,nvptx,174,
GCC,nvptx,175,worker_red_size = GET_MODE_SIZE(SImode) / BITS_PER_UNIT;
GCC,nvptx,176,
GCC,nvptx,177,
GCC,nvptx,178,
GCC,nvptx,179,par -> inner_mask |= GOMP_DIM_MASK ( GOMP_DIM_WORKER ) ;
GCC,nvptx,180,"`if ( par -> mask & GOMP_DIM_MASK ( GOMP_DIM_MAX ) ) nvptx_mpropagate (par -> forked_block, par -> forked_insn);"
GCC,nvptx,181,}
GCC,nvptx,182,
GCC,nvptx,183,"fwrite (asm_out_file, <STR_LIT>, TREE_PURPOSE(dims));"
GCC,nvptx,184,
GCC,nvptx,185,}
GCC,nvptx,186,}
GCC,nvptx,187,
GCC,nvptx,188,
GCC,nvptx,189,
GCC,nvptx,190,
GCC,nvptx,191,}
GCC,nvptx,192,return;
GCC,nvptx,193,
GCC,nvptx,194,
GCC,nvptx,195,
GCC,nvptx,196,<STR_LIT> }
GCC,nvptx,197,
GCC,nvptx,198,}
GCC,nvptx,199,return;
GCC,nvptx,200,
GCC,nvptx,201,"nvptx_assemble_decl_begin ( file , name , section_for_decl ( decl ) , TREE_TYPE ( decl ) , size ? tree_to_shwi ( size ) : <NUM_LIT> , DECL_ALIGN ( decl ) )"
GCC,nvptx,202,"fprintf(file, <STR_LIT>);"
GCC,nvptx,203,if ( ! crtl -> struct_by_value_returns ) {
GCC,nvptx,204,}
GCC,nvptx,205,
GCC,nvptx,206,
GCC,nvptx,207,res = get_insns();
GCC,nvptx,208,
GCC,nvptx,209,"warning_at ( decl ? DECL_SOURCE_LOCATION ( decl ) : UNKNOWN_LOCATION , <NUM_LIT> , dims [ GOMP_DIM_VECTOR ] ? G_ ( <STR_LIT> ) : G_ ( <STR_LIT> ) , PTX_VECTOR_LENGTH , dims [ GOMP_DIM_VECTOR ] ) ;"
GCC,nvptx,210,"diagnose_openacc_conflict ( TARGET_NVPTX_OPT , <STR_LIT> ) ;"
GCC,nvptx,211,
GCC,nvptx,212,"come next. It appears that the code is related to organizing and printing data, specifically around the use of machine registers and stack pointers. Based on the previous statements, it's possible that the next statement could involve further manipulation or output of data using the variables 'bits', 'regno', 'size', 'align', and 'reg_stack'. It's also worth noting that the presence of the 'else' statement and the use of brackets suggests"
GCC,nvptx,213,
GCC,nvptx,214,if ( pars ) {
GCC,nvptx,215,
GCC,nvptx,216,}
GCC,nvptx,217,
GCC,nvptx,218,"init_softstack_frame(file, alignment, sz);"
GCC,nvptx,219,->end_function();
GCC,nvptx,220,return par;
GCC,nvptx,221,"J ( length_mode , data -> <NUM_LIT> , <NUM_LIT> , GEN_INT ( <NUM_LIT> ) );"
GCC,nvptx,222,
GCC,nvptx,223,"split_block ( gsi_bb ( gsi ) , gimple_seq_last ( & seq ) ) ;"
GCC,nvptx,224,gimple_seq inited_seq = NULL ;
GCC,nvptx,225,
GCC,nvptx,226,
GCC,nvptx,227,
GCC,nvptx,228,"else if (rw & PM_modify) emit_insn (gen_rtx_SET (ptr, gen_rtx_MEM (DImode, tmp)));"
GCC,nvptx,229,
GCC,nvptx,230,"oacc_set_fn_attrib ( current_function_decl , attr ) ;"
GCC,nvptx,231,"static bool nvptx_vpropagate (bool is_call, basic_block block, rtx_insn * insn) {"
GCC,nvptx,232,
GCC,nvptx,233,
GCC,nvptx,234,"case NVPTX_BUILTIN_CMP_SWAP : case NVPTX_BUILTIN_CMP_SWAPLL : return nvptx_expand_cmp_swap ( exp , target , mode , ignore ) ;"
GCC,nvptx,235,for (ix = NUM_LIT;
GCC,nvptx,236,
GCC,nvptx,237,
GCC,nvptx,238,"bbsese (unsigned node_, unsigned p, int dir_) : node(node_), parent(p), dir(dir_) {"
GCC,nvptx,239,"This code creates a new instance of the bb_sese class with the given parameters: node, parent, and dir."
GCC,nvptx,240,
GCC,nvptx,241,
GCC,nvptx,242,return res ;
GCC,nvptx,243,
GCC,nvptx,244,return NULL ;
GCC,nvptx,245,
GCC,nvptx,246,return true;
GCC,nvptx,247,else return true;
GCC,nvptx,248,
GCC,nvptx,249,}
GCC,nvptx,250,"worklist.safe_push(insn_bb_t(insn, block));"
GCC,nvptx,251,auto block_seen = map -> get_or_insert ( block );
GCC,nvptx,252,}
GCC,nvptx,253,}
GCC,nvptx,254,"if ( sese -> node < sese -> node + dir && ! ( dir < <NUM_LIT> && sese -> parent == sese -> node ) ) sese -> push ( pseudo_node_t ( sese -> node , usd * <NUM_LIT> ) ) ;"
GCC,nvptx,255,
GCC,nvptx,256,}
GCC,nvptx,257,color = color_counts.get_next();
GCC,nvptx,258,}
GCC,nvptx,259,
GCC,nvptx,260,
GCC,nvptx,261,}
GCC,nvptx,262,if(partition_level > 0) {
GCC,nvptx,263,cfun -> machine -> axis_dim [ MACH_VECTOR_LENGTH ] = oa . vector_length ;
GCC,nvptx,264,else if ( oa . num_workers == <NUM_LIT> ) max_workers = PTX_CTA_SIZE ;
GCC,nvptx,265,"'fprintf ( file , <STR_LIT> , sizeof(align) , reg_names [ regno ] ) ;"
GCC,nvptx,266,
GCC,nvptx,267,"fprintf ( file , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , bits , reg_frame , reg_sspprev , size ) ;"
GCC,nvptx,268,
GCC,nvptx,269,
GCC,nvptx,270,return true;
GCC,nvptx,271,
GCC,nvptx,272,"fprintf ( file , DOC_DECL variable type = %s\n, TYPE_NAME ( type ) ) ;"
GCC,nvptx,273,
GCC,nvptx,274,return ;
GCC,nvptx,275,
GCC,nvptx,276,
GCC,nvptx,277,init_frag . size = elt_size ;
GCC,nvptx,278,
GCC,nvptx,279,init_frag.val = val;
GCC,nvptx,280,"printf(The size of the declaration is %d, size);"
GCC,nvptx,281,
GCC,nvptx,282,}
GCC,nvptx,283,"nvptx_builtin_decl(code+1, ARG_UNUSED(initialize_p));"
GCC,nvptx,284,cfun -> machine -> add_varadic_arg(arg);
GCC,nvptx,285,
GCC,nvptx,286,
GCC,nvptx,287,
GCC,nvptx,288,}
GCC,nvptx,289,
GCC,nvptx,290,
GCC,nvptx,291,"fprintf (file, <STR_LIT>, (type == error_mark_node ? <STR_LIT> : DECL_DEBUG_EXPR(decl) ? <STR_LIT> : DECL_EXTERNAL(decl) ? <STR_LIT> : obj_size));"
GCC,nvptx,292,"fprintf ( file , <STR_LIT> , ( TREE_CHAIN ( decl ) ? <STR_LIT> : TREE_CHAIN ( type ) ? <STR_LIT> : <STR_LIT> ) ) ;"
GCC,nvptx,293,
GCC,nvptx,294,
GCC,nvptx,295,
GCC,nvptx,296,gcc_assert ( pre_insn != BB_HEAD ( pre_block ) ) ;
GCC,nvptx,297,
GCC,nvptx,298,
GCC,nvptx,299,}
GCC,nvptx,300,
GCC,nvptx,301,
GCC,nvptx,302,None ;
GCC,nvptx,303,return cfun->rail ;
GCC,nvptx,304,
GCC,nvptx,305,
GCC,nvptx,306,if (varargs) {
GCC,nvptx,307,"pat = expand_expr ( CALL_EXPR_ARG ( exp , <NUM_LIT> ), NULL_RTX, mode, EXPAND_NORMAL);"
GCC,nvptx,308,"return gen_rtx_fmt_ee (SET_TYPE (compare), BImode, cmp, pred);"
GCC,nvptx,309,
GCC,nvptx,310,
GCC,nvptx,311,}
GCC,nvptx,312,nvptx_barrier_wait (GOMP_BARRIER_HARDWARE) ;
GCC,nvptx,313,return src ;
GCC,nvptx,314,"if ( ! REG_P ( op ) && GET_CODE ( op ) != CONST_INT ) op = copy_to_mode_reg ( SImode , op ) ;"
GCC,nvptx,315,"fputs ( <STR_LIT> , asm_out_file ) ;"
GCC,nvptx,316,"fprintf (asm_out_file, <STR_LIT>, GET_MODE_SIZE(SImode));"
GCC,nvptx,317,
GCC,nvptx,318,}
GCC,nvptx,319,
GCC,nvptx,320,
GCC,nvptx,321,
GCC,nvptx,322,return GET_MODE_SIZE(mode);
GCC,nvptx,323,}
GCC,nvptx,324,printf ( File printed successfully. ) ;
GCC,nvptx,325,return cum->args[i];
GCC,nvptx,326,
GCC,nvptx,327,
GCC,nvptx,328,return true;
GCC,nvptx,329,
GCC,nvptx,330,if(regno >= 0) {
GCC,nvptx,331,}
GCC,nvptx,332,
GCC,nvptx,333,
GCC,nvptx,334,break;
GCC,nvptx,335,
GCC,nvptx,336,}
GCC,nvptx,337,}
GCC,nvptx,338,
GCC,nvptx,339,
GCC,nvptx,340,
GCC,nvptx,341,
GCC,nvptx,342,defines a function called nvptx_globalize_label that takes two parameters: a pointer to a FILE object and a pointer to a string.
GCC,nvptx,343,
GCC,nvptx,344,
GCC,nvptx,345,
GCC,nvptx,346,
GCC,nvptx,347,"bool existed = gang_private_shared_hmap . put ( var , offset ) ;"
GCC,nvptx,348,return true;
GCC,nvptx,349,
GCC,nvptx,350,
GCC,nvptx,351,return var;
GCC,nvptx,352,<NUM_LIT> other_var = make_ssa_name ( TREE_TYPE ( accum ) ) ;
GCC,nvptx,353,"set_immediate_dominator(CDI_DOMINATORS, dst_bb, call_bb);"
GCC,nvptx,354,
GCC,nvptx,355,"if (rhs) gimplify_assign (rhs, var, &seq);"
GCC,nvptx,356,
GCC,nvptx,357,
GCC,nvptx,358,}
GCC,nvptx,359,"error(Declaration type is not void. Cannot add attributes., name);"
GCC,nvptx,360,
GCC,nvptx,361,return 1;
GCC,nvptx,362,
GCC,nvptx,363,
GCC,nvptx,364,Data size in bytes: next
GCC,nvptx,365,"DEF ( END , <STR_LIT> , ( UINT , UINT , UINT , UINT , UINT ) ) ;"
GCC,nvptx,366,
GCC,nvptx,367,return_mode = VOIDmode ;
GCC,nvptx,368,
GCC,nvptx,369,"fprintf ( file , <STR_LIT> ), pred );"
GCC,nvptx,370,break ;
GCC,nvptx,371,
GCC,nvptx,372,
GCC,nvptx,373,if ( fn_class == function_sincos ) {
GCC,nvptx,374,}
GCC,nvptx,375,else if ( nvptx_experimental && mode == SFmode && TARGET_SM53 ) else return false ;
GCC,nvptx,376,
GCC,nvptx,377,"* gsi_stmt(*gsi) = gimple_build_call(fndecl, <argument>, <argument>);"
GCC,nvptx,378,
GCC,nvptx,379,return -1;
GCC,nvptx,380,
GCC,nvptx,381,}
GCC,nvptx,382,
GCC,nvptx,383,
GCC,nvptx,384,
GCC,nvptx,385,}
GCC,nvptx,386,
GCC,nvptx,387,}
GCC,nvptx,388,if (area == DATA_AREA_SHARED || area == DATA_AREA_GENERIC) {
GCC,nvptx,389,if (!found) {
GCC,nvptx,390,
GCC,nvptx,391,"if ( strcmp ( name , <STR_LIT> ) == <NUM_LIT> ) return <STR_LIT> ;"
GCC,nvptx,392,
GCC,nvptx,393,bool cluster = mask & GOMP_DIM_MASK ( GOMP_DIM_CLUSTER ) ;
GCC,nvptx,394,if ( skip_mask ) {
GCC,nvptx,395,
GCC,nvptx,396,Par->inner = join->inner;
GCC,nvptx,397,if ( nvptx_optimize < <NUM_LIT> ) nvptx_optimize = optimize > <NUM_LIT> ;
GCC,nvptx,398,"diagnose_openacc_conflict ( TARGET_ARB_DATA , <STR_LIT> ) ;"
GCC,nvptx,399,"write_var_marker(file, false, false, name);"
GCC,nvptx,400,"nvptx_output_control_flow_insn(&operands[neg_pos], int_val(operands[cond_pos]), false);"
GCC,nvptx,401,if (pre_p || post_p) break;
GCC,nvptx,402,}
GCC,nvptx,403,var asm_out_file = [CONCAT:String]var output [CONCAT:String] [CONCAT:String] fnt procs [CONCAT:String]varhawkV10 [CONCAT:String]erre fs
GCC,nvptx,404,
GCC,nvptx,405,
GCC,nvptx,406,return <STR_LIT>;
GCC,nvptx,407,
GCC,nvptx,408,return nvptx_softstack:: }
GCC,nvptx,409,
GCC,nvptx,410,
GCC,nvptx,411,
GCC,nvptx,412,}
GCC,nvptx,413,
GCC,nvptx,414,if (arg.passed_by_reference) {
GCC,nvptx,415,pat = PATTERN ( insn ) ;
GCC,nvptx,416,
GCC,nvptx,417,
GCC,nvptx,418,
GCC,nvptx,419,}
GCC,nvptx,420,break ;
GCC,nvptx,421,
GCC,nvptx,422,
GCC,nvptx,423,
GCC,nvptx,424,
GCC,nvptx,425,}
GCC,nvptx,426,return mode;
GCC,nvptx,427,
GCC,nvptx,428,}
GCC,nvptx,429,case E_TImode : return <STR_LIT> ;
GCC,nvptx,430,
GCC,nvptx,431,else {
GCC,nvptx,432,"printf(Function name: %s, name);"
GCC,nvptx,433,return 1;
GCC,nvptx,434,if (slot != NULL) {
GCC,nvptx,435,}
GCC,nvptx,436,return 0;
GCC,nvptx,437,<STR_LIT> }
GCC,nvptx,438,
GCC,nvptx,439,
GCC,nvptx,440,
GCC,nvptx,441,
GCC,nvptx,442,
GCC,nvptx,443,
GCC,nvptx,444,
GCC,nvptx,445,
GCC,nvptx,446,}
GCC,nvptx,447,edges->quick_push(b);
GCC,nvptx,448,
GCC,nvptx,449,child = nullptr ;
GCC,nvptx,450,error: unexpected token 'vector_red_partition'
GCC,nvptx,451,"oacc_bcast_offset = MAX(oacc_bcast_offset, psize * (pnum - 1));"
GCC,nvptx,452,"rtx gen_rtx_SET ( data . base , bcast_sym );"
GCC,nvptx,453,}
GCC,nvptx,454,
GCC,nvptx,455,
GCC,nvptx,456,printf(Execution completed successfully.);
GCC,nvptx,457,tail->next = NULL;
GCC,nvptx,458,"worklist.safe_push (insn_bb_t (insn, block)) because else map -> get_or_insert (block) = insn;"
GCC,nvptx,459,}
GCC,nvptx,460,
GCC,nvptx,461,}
GCC,nvptx,462,return true;
GCC,nvptx,463,the end curly brace }
GCC,nvptx,464,"emit_insn_after ( nvptx_load_reg_plus ( GET_MODE ( reg ) , reg , master , const0 ) , insn ) ;"
GCC,nvptx,465,}
GCC,nvptx,466,return false;
GCC,nvptx,467,
GCC,nvptx,468,return align;
GCC,nvptx,469,
GCC,nvptx,470,
GCC,nvptx,471,}
GCC,nvptx,472,}
GCC,nvptx,473,else {
GCC,nvptx,474,"printf (asm_out_file, <STR_LIT>);"
GCC,nvptx,475,
GCC,nvptx,476,}
GCC,nvptx,477,
GCC,nvptx,478,
GCC,nvptx,479,case <NUM_LIT+1>: which would be one of the next possible cases in the switch statement.
GCC,nvptx,480,
GCC,nvptx,481,if (mode == SImode ) mode = DImode;
GCC,nvptx,482,
GCC,nvptx,483,}
GCC,nvptx,484,}
GCC,nvptx,485,gcc_unreachable( );
GCC,nvptx,486,brackets . safe_push ( bracket ( back ) ) ;
GCC,nvptx,487,break ;
GCC,nvptx,488,
GCC,nvptx,489,
GCC,nvptx,490,if (first > last) {
GCC,nvptx,491,
GCC,nvptx,492,
GCC,nvptx,493,
GCC,nvptx,494,
GCC,nvptx,495,
GCC,nvptx,496,gcc_assert (seen_vector_label || seen_worker_label);
GCC,nvptx,497,break;
GCC,nvptx,498,
GCC,nvptx,499,
GCC,nvptx,500,"return propagate_delay_slots(reg, pm);"
GCC,nvptx,501,
GCC,nvptx,502,
GCC,nvptx,503,the closing curly brace (}
GCC,nvptx,504,workaround_uninit_method_3();
GCC,nvptx,505,}
GCC,nvptx,506,
GCC,nvptx,507,set_redirect-return ( reg ) }
GCC,nvptx,508,
GCC,nvptx,509,end_sequence ( ) ;
GCC,nvptx,510,}
GCC,nvptx,511,
GCC,nvptx,512,}
GCC,nvptx,513,s << <STR_LIT> << ( is_defn ? <STR_LIT> : <STR_LIT> ) ;
GCC,nvptx,514,
GCC,nvptx,515,else if (replaced_dots != NULL) {
GCC,nvptx,516,
GCC,nvptx,517,"if (result != NULL_RTX) write_return_mode (s, true, GET_MODE(result));"
GCC,nvptx,518,s << <STR_LIT> ;
GCC,nvptx,519,s << pfx << ptx_type << <STR_LIT> << reg_names [ NVPTX_RETURN_REGNUM ] << sfx ;
GCC,nvptx,520,
GCC,nvptx,521,}
GCC,nvptx,522,
GCC,nvptx,523,
GCC,nvptx,524,
GCC,nvptx,525,return 0;
GCC,nvptx,526,
GCC,riscv,0,
GCC,riscv,1,mode << <STR_LIT> << mlen << <STR_LIT> ;
GCC,riscv,2,
GCC,riscv,3,
GCC,riscv,4,
GCC,riscv,5,return lmul_str;
GCC,riscv,6,case <NUM_LIT> : return lmul_log2 >= <NUM_LIT> && !float_p ;
GCC,riscv,7,tree frflags = GET_BUILTIN_DECL ( CODE_FOR_riscv_fsflags ) ;
GCC,riscv,8,if ( subcode >= ARRAY_SIZE ( riscv_builtins ) ) return error_mark_node ;
GCC,riscv,9,"return riscv_expand_builtin_direct(d->icode, target, exp, false);"
GCC,riscv,10,"printf(RISC-V builtin function at index %ld is %s\n, i, riscv_builtins[i]);"
GCC,riscv,11,
GCC,riscv,12,}
GCC,riscv,13,
GCC,riscv,14,"return riscv_expand_builtin_direct (riscv_expand_builtin_direct  (ICODE_SIGNBITP, target, exp, false));"
GCC,riscv,15,return d->insn;
GCC,riscv,16,
GCC,riscv,17,enum insn_code icode = d -> icode ;
GCC,riscv,18,return NULL_RTX ;
GCC,riscv,19,
GCC,riscv,20,
GCC,riscv,21,
GCC,riscv,22,
GCC,riscv,23,
GCC,riscv,24,"riscv_prepare_builtin_arg ( & ops [ opno ++ ] , exp , argno + 1 ) ;"
GCC,riscv,25,
GCC,riscv,26,
GCC,riscv,27,
GCC,riscv,28,
GCC,riscv,29,}
GCC,riscv,30,
GCC,riscv,31,
GCC,riscv,32,
GCC,riscv,33,break ;
GCC,riscv,34,
GCC,riscv,35,abi = <STR_LIT> ;
GCC,riscv,36,
GCC,riscv,37,
GCC,riscv,38,if (TARGET_RVV) d_add_builtin_version(<STR_LIT>);
GCC,riscv,39,"return eval_value(reg, regno_to_rtx);"
GCC,riscv,40,
GCC,riscv,41,"ASSERT_TRUE ( rtx_equal_p ( src , CONST0_RTX ( mode ) ) ) ;"
GCC,riscv,42,
GCC,riscv,43,
GCC,riscv,44,
GCC,riscv,45,
GCC,riscv,46,end_sequence();
GCC,riscv,47,
GCC,riscv,48,
GCC,riscv,49,
GCC,riscv,50,return global_options.arch;
GCC,riscv,51,
GCC,riscv,52,}
GCC,riscv,53,}
GCC,riscv,54,}
GCC,riscv,55,}
GCC,riscv,56,}
GCC,riscv,57,
GCC,riscv,58,"XEXP ( pat , i ) = replace_equiv_address ( mem , addr ) ;"
GCC,riscv,59,
GCC,riscv,60,return optimize > <NUM_LIT> + 1 ;
GCC,riscv,61,
GCC,riscv,62,false;
GCC,riscv,63,"return REG_P ( XEXP ( * addr , <NUM_LIT> ) ) ;"
GCC,riscv,64,return new shorten_memrefs_pass ( ctxt ) ;
GCC,riscv,65,"appears to define a function or method called pass_shorten_memrefs that takes a parameter ctxt of type gcc :: context * and extends the rtl_opt_pass class or structure with the attributes pass_data_shorten_memrefs and ctxt. The next statement may be a body or implementation of this function, which could include instructions or logic for optimizing memory references."
GCC,riscv,66,return new shorten_memrefs_pass ( ctxt );
GCC,riscv,67,else {
GCC,riscv,68,
GCC,riscv,69,<x> }
GCC,riscv,70,}
GCC,riscv,71,
GCC,riscv,72,}
GCC,riscv,73,
GCC,riscv,74,rtx_insn * parent = PREV_INSN ( call );
GCC,riscv,75,if ( NOTE_P ( insn ) ) {
GCC,riscv,76,
GCC,riscv,77,}
GCC,riscv,78,return true;
GCC,riscv,79,
GCC,riscv,80,
GCC,riscv,81,CP_EXECUTE_FUNCTION ;
GCC,riscv,82,
GCC,riscv,83,
GCC,riscv,84,if (mode == MACHINE_MODE_64BIT) {
GCC,riscv,85,"return e.expand_vector_libcall (libcall_expand (e.target, bds, rtx_TEMP, vlenb));"
GCC,riscv,86,
GCC,riscv,87,
GCC,riscv,88,
GCC,riscv,89,}
GCC,riscv,90,}
GCC,riscv,91,"b.set_shape(, , int);"
GCC,riscv,92,
GCC,riscv,93,
GCC,riscv,94,"auto_vec < tree , <NUM_LIT> > return_values;"
GCC,riscv,95,
GCC,riscv,96,"return c . require_immediate ( num , num , nvecs - 1 ) ;"
GCC,riscv,97,b.finish_name();
GCC,riscv,98,add_label ( L1 ) ;
GCC,riscv,99,}
GCC,riscv,100,
GCC,riscv,101,
GCC,riscv,102,return rfn;
GCC,riscv,103,}
GCC,riscv,104,
GCC,riscv,105,"create_integer_operand (&m_ops [opno++], INTVAL(x));"
GCC,riscv,106,
GCC,riscv,107,return mem;
GCC,riscv,108,"create_output_operand(&m_ops[opno++], target, mode);"
GCC,riscv,109,
GCC,riscv,110,
GCC,riscv,111,"TYPE_ATTRIBUTES (type) = tree_cons (get_identifier (<STR_LIT>) , value , TYPE_ATTRIBUTES (type)) ;"
GCC,riscv,112,
GCC,riscv,113,i < 5 ;
GCC,riscv,114,
GCC,riscv,115,
GCC,riscv,116,append_name ( another_name ) ;
GCC,riscv,117,}
GCC,riscv,118,
GCC,riscv,119,obstack finish (&m_string_obstack);
GCC,riscv,120,
GCC,riscv,121,}
GCC,riscv,122,}
GCC,riscv,123,
GCC,riscv,124,
GCC,riscv,125,}
GCC,riscv,126,
GCC,riscv,127,
GCC,riscv,128,
GCC,riscv,129,}
GCC,riscv,130,
GCC,riscv,131,}
GCC,riscv,132,}
GCC,riscv,133,end with the statement return true;
GCC,riscv,134,"return rfn.check_args ( nargs , args ) ;"
GCC,riscv,135,}
GCC,riscv,136,return false ;
GCC,riscv,137,return ( flags &amp;
GCC,riscv,138,return (hash(value) == hash(key));
GCC,riscv,139,
GCC,riscv,140,
GCC,riscv,141,
GCC,riscv,142,
GCC,riscv,143,
GCC,riscv,144,
GCC,riscv,145,m_direct_overloads = m_direct_overloads + 1;
GCC,riscv,146,}
GCC,riscv,147,
GCC,riscv,148,return fndecl;
GCC,riscv,149,
GCC,riscv,150,
GCC,riscv,151,
GCC,riscv,152,
GCC,riscv,153,}
GCC,riscv,154,if (  args ) {
GCC,riscv,155,return NULL;
GCC,riscv,156,
GCC,riscv,157,
GCC,riscv,158,}
GCC,riscv,159,if (type != NUM_VECTOR_TYPES) {
GCC,riscv,160,if (type) {
GCC,riscv,161,
GCC,riscv,162,
GCC,riscv,163,instance.process();
GCC,riscv,164,
GCC,riscv,165,
GCC,riscv,166,else return builtin_types [ VECTOR_TYPE_vuint8m1_t ] . scalar_ptr ;
GCC,riscv,167,
GCC,riscv,168,
GCC,riscv,169,
GCC,riscv,170,
GCC,riscv,171,if ( pred == PRED_TYPE_tu || pred == PRED_TYPE_tum || pred == PRED_TYPE_tumu ) {
GCC,riscv,172,
GCC,riscv,173,Possible options:
GCC,riscv,174,
GCC,riscv,175,return;
GCC,riscv,176,
GCC,riscv,177,"return gimple_build_call (gimple_location (gsi), code, gimple_call_fn (stmt), gimple_call_fnargs (stmt), false, NULL_TREE);"
GCC,riscv,178,
GCC,riscv,179,s: return;
GCC,riscv,180,}
GCC,riscv,181,
GCC,riscv,182,}
GCC,riscv,183,builder.produce(function_table);
GCC,riscv,184,
GCC,riscv,185,
GCC,riscv,186,
GCC,riscv,187,
GCC,riscv,188,if (rvv_switcher == true) {
GCC,riscv,189,
GCC,riscv,190,
GCC,riscv,191,if (type == NULL) {
GCC,riscv,192,if ( id != NULL) printf(The identifier pointer id is not null.);
GCC,riscv,193,
GCC,riscv,194,
GCC,riscv,195,
GCC,riscv,196,
GCC,riscv,197,return flags & ACCESS_READS_GLOBAL_STATE;
GCC,riscv,198,
GCC,riscv,199,
GCC,riscv,200,tree uint16_type_node = get_typenode_from_name ( UINT16_TYPE ) ;
GCC,riscv,201,
GCC,riscv,202,
GCC,riscv,203,
GCC,riscv,204,
GCC,riscv,205,
GCC,riscv,206,
GCC,riscv,207,}
GCC,riscv,208,tree_fits_shwi_p ( arg ) ;
GCC,riscv,209,}
GCC,riscv,210,
GCC,riscv,211,
GCC,riscv,212,
GCC,riscv,213,{
GCC,riscv,214,if ( is_rvv_base_type_char ( base_type_in )) {
GCC,riscv,215,
GCC,riscv,216,
GCC,riscv,217,
GCC,riscv,218,return 0;
GCC,riscv,219,
GCC,riscv,220,
GCC,riscv,221,
GCC,riscv,222,}
GCC,riscv,223,}
GCC,riscv,224,"An rtx vs3 = expand_normal ( CALL_EXPR_ARG (exp, arg_offset++) );"
GCC,riscv,225,
GCC,riscv,226,
GCC,riscv,227,inline machine mode function expander :: vector mode ( void ) const {
GCC,riscv,228,
GCC,riscv,229,
GCC,riscv,230,if ( LABEL_P ( label_ref_label ( x ) ) ) LABEL_NUSES ( label_ref_label ( x ) ) ++ ;
GCC,riscv,231,
GCC,riscv,232,return true;
GCC,riscv,233,return true;
GCC,riscv,234,return false;
GCC,riscv,235,return false;
GCC,riscv,236,if ( set_vlval ( dest ) ) {
GCC,riscv,237,
GCC,riscv,238,return hash_value > other.hash_value;
GCC,riscv,239,return m_value;
GCC,riscv,240,
GCC,riscv,241,
GCC,riscv,242,gcc_assert(block_info.reaching_out.valid_p());
GCC,riscv,243,}
GCC,riscv,244,
GCC,riscv,245,}
GCC,riscv,246,
GCC,riscv,247,if ( m_vector_manager -> vector_exprs [ expr_id ] -> all_same_ratio_p ( m_vector_manager -> vector_avout [ e -> src -> index ] ) ) return false ;
GCC,riscv,248,if ( all_valid_p == false ) throw new InvalidVLException();
GCC,riscv,249,
GCC,riscv,250,rinsn = insn->rtl();
GCC,riscv,251,return changed_p;
GCC,riscv,252,auto attempt = crtl->ssa->new_change_attempt();
GCC,riscv,253,}
GCC,riscv,254,
GCC,riscv,255,
GCC,riscv,256,
GCC,riscv,257,
GCC,riscv,258,
GCC,riscv,259,if ( demand_p ( DEMAND_NONZERO_AVL ) && other . has_non_zero_avl ( ) ) {
GCC,riscv,260,
GCC,riscv,261,
GCC,riscv,262,
GCC,riscv,263,}
GCC,riscv,264,new_prob = curr_prob * crtl -> ssa -> probabilities [ e -> dest ] ;
GCC,riscv,265,the following: if (curr_prob >= 0.5) break;
GCC,riscv,266,
GCC,riscv,267,"bitmap_vector_ones ( vector_comp , last_basic_block_for_fn ( cfun ) ) ;"
GCC,riscv,268,return info;
GCC,riscv,269,
GCC,riscv,270,
GCC,riscv,271,M_demands [ type + 1 ] = true ;
GCC,riscv,272,}
GCC,riscv,273,return false;
GCC,riscv,274,
GCC,riscv,275,
GCC,riscv,276,return false;
GCC,riscv,277,
GCC,riscv,278,
GCC,riscv,279,
GCC,riscv,280,
GCC,riscv,281,
GCC,riscv,282,
GCC,riscv,283,
GCC,riscv,284,"FOR_ALL_BB_FN (cfg_bb, cfun) {"
GCC,riscv,285,"print_rtl_sequence ( dump_file , rinsn ) ;"
GCC,riscv,286,}
GCC,riscv,287,"if ( emit_type == EMIT_AFTER ) emit_insn_after ( pat , rinsn ) ;"
GCC,riscv,288,
GCC,riscv,289,}
GCC,riscv,290,return 0;
GCC,riscv,291,cout << There are  << count <<  items in the collection.;
GCC,riscv,292,
GCC,riscv,293,
GCC,riscv,294,}
GCC,riscv,295,return info1.get_ratio();
GCC,riscv,296,
GCC,riscv,297,
GCC,riscv,298,return info;
GCC,riscv,299,m_vector_manager -> to_delete_vsetvls . add ( insn -> rtl ( ) ) ;
GCC,riscv,300,
GCC,riscv,301,vector_kill = nullptr;
GCC,riscv,302,"either  to end the innermost if statement, or a new line beginning with }"
GCC,riscv,303,set_avl_info ( info1 . get_avl_info ( ) ) ;
GCC,riscv,304,
GCC,riscv,305,
GCC,riscv,306,set_ta ( info2 . get_ta ( ) ) ;
GCC,riscv,307,}
GCC,riscv,308,
GCC,riscv,309,}
GCC,riscv,310,
GCC,riscv,311,
GCC,riscv,312,}
GCC,riscv,313,auto_vec < basic_block > next_block = work_list . pop ( ) ;
GCC,riscv,314,
GCC,riscv,315,
GCC,riscv,316,return avl_info;
GCC,riscv,317,
GCC,riscv,318,
GCC,riscv,319,if ( may_cause_fault_on_load ( i ) ) {
GCC,riscv,320,}
GCC,riscv,321,
GCC,riscv,322,
GCC,riscv,323,
GCC,riscv,324,}
GCC,riscv,325,return <NUM_LIT> ;
GCC,riscv,326,}
GCC,riscv,327,
GCC,riscv,328,cout << Throwing a runtime error;
GCC,riscv,329,return vector_insn_info();
GCC,riscv,330,
GCC,riscv,331,}
GCC,riscv,332,
GCC,riscv,333,
GCC,riscv,334,
GCC,riscv,335,
GCC,riscv,336,
GCC,riscv,337,}
GCC,riscv,338,
GCC,riscv,339,
GCC,riscv,340,socket.getState() }
GCC,riscv,341,
GCC,riscv,342,return info;
GCC,riscv,343,}
GCC,riscv,344,
GCC,riscv,345,
GCC,riscv,346,
GCC,riscv,347,
GCC,riscv,348,
GCC,riscv,349,
GCC,riscv,350,}
GCC,riscv,351,return false;
GCC,riscv,352,"return the maximum value between the sew values of two info objects, using the std::max function."
GCC,riscv,353,
GCC,riscv,354,}
GCC,riscv,355,
GCC,riscv,356,
GCC,riscv,357,return m_reg == 0 && m_avl;
GCC,riscv,358,
GCC,riscv,359,
GCC,riscv,360,
GCC,riscv,361,return false;
GCC,riscv,362,
GCC,riscv,363,}
GCC,riscv,364,return true;
GCC,riscv,365,
GCC,riscv,366,
GCC,riscv,367,
GCC,riscv,368,}
GCC,riscv,369,}
GCC,riscv,370,
GCC,riscv,371,if ( JUMP_P ( pat ) || ( NONJUMP_INSN_P ( pat ) && ( ! single_succ_p ( cfg_bb ) || single_succ_edge ( cfg_bb ) -> flags & EDGE_ABNORMAL ) ) ) {
GCC,riscv,372,
GCC,riscv,373,
GCC,riscv,374,"if ( dump_file ) fprintf ( dump_file , <STR_LIT> ) ;"
GCC,riscv,375,return true;
GCC,riscv,376,
GCC,riscv,377,}
GCC,riscv,378,'}
GCC,riscv,379,
GCC,riscv,380,ma = get_attr_ma ( rinsn );
GCC,riscv,381,
GCC,riscv,382,
GCC,riscv,383,
GCC,riscv,384,
GCC,riscv,385,
GCC,riscv,386,if (has_vl_op(insn->rtl())) m_demands[DEMAND_AVL] = true;
GCC,riscv,387,
GCC,riscv,388,
GCC,riscv,389,
GCC,riscv,390,
GCC,riscv,391,
GCC,riscv,392,
GCC,riscv,393,std :: ostream & dump_file = *dump_file ;
GCC,riscv,394,
GCC,riscv,395,}
GCC,riscv,396,
GCC,riscv,397,continue;
GCC,riscv,398,
GCC,riscv,399,if (def_insn->regs_read().find(reg) != def_insn->regs_read().end()) return true;
GCC,riscv,400,
GCC,riscv,401,
GCC,riscv,402,
GCC,riscv,403,
GCC,riscv,404,
GCC,riscv,405,
GCC,riscv,406,}
GCC,riscv,407,
GCC,riscv,408,
GCC,riscv,409,return info2.ratio;
GCC,riscv,410,return info2;
GCC,riscv,411,
GCC,riscv,412,
GCC,riscv,413,
GCC,riscv,414,
GCC,riscv,415,
GCC,riscv,416,"return vlmul_type(info2.vlen(), info2.clmul2x2());"
GCC,riscv,417,
GCC,riscv,418,}
GCC,riscv,419,}
GCC,riscv,420,
GCC,riscv,421,
GCC,riscv,422,
GCC,riscv,423,}
GCC,riscv,424,cerr << Hard drive is now empty.;
GCC,riscv,425,
GCC,riscv,426,
GCC,riscv,427,
GCC,riscv,428,
GCC,riscv,429,
GCC,riscv,430,}
GCC,riscv,431,
GCC,riscv,432,
GCC,riscv,433,
GCC,riscv,434,}
GCC,riscv,435,cout << The value of m_vlmul is now  << m_vlmul << endl;
GCC,riscv,436,
GCC,riscv,437,
GCC,riscv,438,if (insn2 == NULL) return false;
GCC,riscv,439,
GCC,riscv,440,
GCC,riscv,441,Int t = get_attr_t ( rinsn ) ;
GCC,riscv,442,return ta == INVALID_ATTRIBUTE ? get_default_ta ( ) : IS_AGNOSTIC ( ta ) ;
GCC,riscv,443,
GCC,riscv,444,
GCC,riscv,445,
GCC,riscv,446,
GCC,riscv,447,}
GCC,riscv,448,
GCC,riscv,449,set_insn ( insn ) ;
GCC,riscv,450,
GCC,riscv,451,
GCC,riscv,452,
GCC,riscv,453,
GCC,riscv,454,
GCC,riscv,455,<e> if (DEBUG_EMPTY_PAT (&amp;
GCC,riscv,456,return ((rinsn != NULL) && (GET_CODE (rinsn) == CODE );
GCC,riscv,457,
GCC,riscv,458,
GCC,riscv,459,m_num_demands = 0;
GCC,riscv,460,
GCC,riscv,461,return rinsn != NULL || rinsn->src != NULL;
GCC,riscv,462,
GCC,riscv,463,
GCC,riscv,464,
GCC,riscv,465,return m_ma;
GCC,riscv,466,
GCC,riscv,467,
GCC,riscv,468,a conditional statement or another function call that uses the returned value as a condition. For example: if (( INSN_CODE ( rinsn ) == CODE_FOR_vsetvldi || INSN_CODE ( rinsn ) == CODE_FOR_vsetvlsi ) {
GCC,riscv,469,"<reference>: add_constraint ( CONSTRAINT, 1 , GE ) ;"
GCC,riscv,470,
GCC,riscv,471,
GCC,riscv,472,"_add_operation (tail_policy_rtx, mask_policy_rtx, Pmode);"
GCC,riscv,473,
GCC,riscv,474,The next statement might be something like:
GCC,riscv,475,return;
GCC,riscv,476,case <NUM_LIT> :<NUM_LIT> = sew / <NUM_LIT> ;
GCC,riscv,477,
GCC,riscv,478,
GCC,riscv,479,
GCC,riscv,480,
GCC,riscv,481,"emit_nvlmax_op(icode, NULL_RTX, dest, src, len, mask_mode, true);"
GCC,riscv,482,
GCC,riscv,483,e.add_vundef_operand(mode);
GCC,riscv,484,
GCC,riscv,485,"emit_pred_op (icode, NULL_RTX, dest, src, len, mask_mode, false);"
GCC,riscv,486,
GCC,riscv,487,if (optimize) {
GCC,riscv,488,
GCC,riscv,489,}
GCC,riscv,490,
GCC,riscv,491,}
GCC,riscv,492,}
GCC,riscv,493,
GCC,riscv,494,
GCC,riscv,495,
GCC,riscv,496,builder . quick_push ( const2_rtx ) ;
GCC,riscv,497,
GCC,riscv,498,return (float) (j * ma);
GCC,riscv,499,return ma & MASK;
GCC,riscv,500,
GCC,riscv,501,return mask_policy;
GCC,riscv,502,}
GCC,riscv,503,
GCC,riscv,504,
GCC,riscv,505,return SEW[mode];
GCC,riscv,506,
GCC,riscv,507,}
GCC,riscv,508,
GCC,riscv,509,
GCC,riscv,510,
GCC,riscv,511,
GCC,riscv,512,i32vl = gen_reg_rtx (Pmode);
GCC,riscv,513,
GCC,riscv,514,case LTU : case CS: return cast_pointer_to_uint ( x ) ;
GCC,riscv,515,
GCC,riscv,516,return m_opno * 2;
GCC,riscv,517,"return emit_move_insn ( tmp , src ) && emit_move_insn ( dest , tmp ) ;"
GCC,riscv,518,"emit_vlmax_op ( code_for_pred_mov ( mode ) , src , dest , mask_mode ) ;"
GCC,riscv,519,vlmul_for_min_vlen32 [ MODE ## mode ] = VLMUL_FOR_MIN_VLEN32 ;
GCC,riscv,520,else if ( INTVAL ( x ) < 0x8000 && INTVAL ( x ) >= -0x8000 ) return true ;
GCC,riscv,521,}
GCC,riscv,522,
GCC,riscv,523,
GCC,riscv,524,
GCC,riscv,525,
GCC,riscv,526,ops [ < NUM_LIT > ] = demote_scalar_op1;
GCC,riscv,527,
GCC,riscv,528,
GCC,riscv,529,
GCC,riscv,530,
GCC,riscv,531,
GCC,riscv,532,
GCC,riscv,533,
GCC,riscv,534,"riscv_block_move_loop(dest, src, length, bytes_per_iter);"
GCC,riscv,535,
GCC,riscv,536,extern const <NUM_LIT> riscv_max_nshift = <NUM_LIT> * <NUM_LIT> - <NUM_LIT>;
GCC,riscv,537,else{
GCC,riscv,538,if (GET_CODE(x) == LOW) return false;
GCC,riscv,539,
GCC,riscv,540,return riscv_valid_base_commandes:
GCC,riscv,541,case CONST_INT :.
GCC,riscv,542,
GCC,riscv,543,
GCC,riscv,544,
GCC,riscv,545,if ( TARGET_HARD_FLOAT && TARGET_ABIVERSION_ <NUM_LIT> ) {
GCC,riscv,546,for ( int regno = FP_REG_FIRST ;
GCC,riscv,547,for ( int regno = 0;
GCC,riscv,548,riscv_bytes_per_vector_chunk = TARGET_MIN_VLEN <NUM_LIT> ;
GCC,riscv,549,
GCC,riscv,550,
GCC,riscv,551,return s;
GCC,riscv,552,
GCC,riscv,553,}
GCC,riscv,554,
GCC,riscv,555,
GCC,riscv,556,}
GCC,riscv,557,
GCC,riscv,558,
GCC,riscv,559,
GCC,riscv,560,
GCC,riscv,561,
GCC,riscv,562,"gcc_assert (reg_or_0_operand (cons, mode));"
GCC,riscv,563,if (GET_CODE(cond) == EQ) {
GCC,riscv,564,REG_NOTES ( insn ) = dwarf ;
GCC,riscv,565,emit_insn ( riscv_normalize_stack_address ( frame ) ) ;
GCC,riscv,566,
GCC,riscv,567,"pat = gen_rtx_fmt_e ( code , mode , op1 ) ;"
GCC,riscv,568,"emit_insn ( gen_rtx_SET ( op0 , pat ) ) ;"
GCC,riscv,569,scalable_frame . m = size . host_to_poly ( ) ;
GCC,riscv,570,}
GCC,riscv,571,}
GCC,riscv,572,"if ( !riscv_mrelax && riscv_mcsr_check ) fprintf ( asm_out_file , <STR_LIT> ) ;"
GCC,riscv,573,
GCC,riscv,574,"If TARGET_RVC is true and min_second_step is in the range [<NUM_LIT>, (TARGET_64BIT ? SDSP_REACH : SWSP_REACH)], then return the maximum of min_second_step and min_first_step;"
GCC,riscv,575,n ++ ;
GCC,riscv,576,"riscv_save_restore_reg ( word_mode , regno , offset , fn ) ;"
GCC,riscv,577,
GCC,riscv,578,
GCC,riscv,579,
GCC,riscv,580,
GCC,riscv,581,if ( ! TARGET_64BIT && TARGET_ZDINX ) {
GCC,riscv,582,else return true;
GCC,riscv,583,return (GET_MODE_SIZE(mode).to_constant() + UNITS_PER_WORD - <NUM_LIT>) / UNITS_PER_WORD;
GCC,riscv,584,- return src - dest ;
GCC,riscv,585,
GCC,riscv,586,"set_optab_libfunc (gt_optab, HFmode, NULL);"
GCC,riscv,587,
GCC,riscv,588,}
GCC,riscv,589,"reg = force_reg ( mode , src ) ;"
GCC,riscv,590,}
GCC,riscv,591,
GCC,riscv,592,
GCC,riscv,593,if (TYPE_SIZE(type) == <INT_LIT>) return <BOOL_LIT>;
GCC,riscv,594,break;
GCC,riscv,595,
GCC,riscv,596,}
GCC,riscv,597,return INVALID_REGNUM ;
GCC,riscv,598,return <STR_LIT> ;
GCC,riscv,599,else {
GCC,riscv,600,break ;
GCC,riscv,601,cfun->machine->frame.fp_pc_offset = offset;
GCC,riscv,602,return mode;
GCC,riscv,603,return type;
GCC,riscv,604,
GCC,riscv,605,else return 0;
GCC,riscv,606,execute_machine_code();
GCC,riscv,607,enable_machine_modes ( ) ;
GCC,riscv,608,
GCC,riscv,609,
GCC,riscv,610,return true ;
GCC,riscv,611,
GCC,riscv,612,
GCC,riscv,613,
GCC,riscv,614,
GCC,riscv,615,
GCC,riscv,616,
GCC,riscv,617,"next_slot_address = riscv_add_offset (scratch, stack_pointer_rtx, cfun->machine->frame.gp_sp_offset.to_constant()) ;"
GCC,riscv,618,
GCC,riscv,619,
GCC,riscv,620,riscv_finish_move ();
GCC,riscv,621,
GCC,riscv,622,
GCC,riscv,623,return true;
GCC,riscv,624,}
GCC,riscv,625,return true;
GCC,riscv,626,
GCC,riscv,627,if (min_size < 0) printf(Error: Invalid size!);
GCC,riscv,628,
GCC,riscv,629,
GCC,riscv,630,}
GCC,riscv,631,
GCC,riscv,632,return riscv_v_vector_chunks * scale;
GCC,riscv,633,"return riscv_v_precision_adjusted(mode, scale);"
GCC,riscv,634,
GCC,riscv,635,
GCC,riscv,636,return false;
GCC,riscv,637,
GCC,riscv,638,}
GCC,riscv,639,
GCC,riscv,640,
GCC,riscv,641,
GCC,riscv,642,
GCC,riscv,643,
GCC,riscv,644,
GCC,riscv,645,None;
GCC,riscv,646,
GCC,riscv,647,"rtx frame_address = gen_rtx_FRAME_ADDR (dwarf, adjust_sp_rtx, reg, saved_size);"
GCC,riscv,648,
GCC,riscv,649,
GCC,riscv,650,arg = 0;
GCC,riscv,651,}
GCC,riscv,652,alt_codes [ alt_cost - <NUM_LIT> ] . code = ASHIFT ;
GCC,riscv,653,if (flag_pic) return true;
GCC,riscv,654,default : break ;
GCC,riscv,655,}
GCC,riscv,656,}
GCC,riscv,657,
GCC,riscv,658,info->const = const0_rtx;
GCC,riscv,659,"else return riscv_hard_regno_nregs (FP_REG_FIRST, mode) ;"
GCC,riscv,660,frame -> return_address_offset = offset ;
GCC,riscv,661,CONDITIONAL = TRUE;
GCC,riscv,662,
GCC,riscv,663,* code = EQ ;
GCC,riscv,664,"likely part of a larger function, so the next statement could vary depending on the context. However, based on the current structure, the next statement is likely: }"
GCC,riscv,665,step1 += step2 ;
GCC,riscv,666,
GCC,riscv,667,
GCC,riscv,668,}
GCC,riscv,669,}
GCC,riscv,670,
GCC,riscv,671,}
GCC,riscv,672,
GCC,riscv,673,
GCC,riscv,674,"return riscv_flatten_aggregate_field (type, fields, <NUM_LIT>, <NUM_LIT+1>);"
GCC,riscv,675,fields[0].type = TREE_TYPE(type);
GCC,riscv,676,
GCC,riscv,677,return x;
GCC,riscv,678,"return gen_rtx_fmt_ee (code, mode, x, y);"
GCC,riscv,679,
GCC,riscv,680,
GCC,riscv,681,
GCC,riscv,682,
GCC,riscv,683,
GCC,riscv,684,
GCC,riscv,685,
GCC,riscv,686,
GCC,riscv,687,= TYPE_UNSIGNED (type);
GCC,riscv,688,"return gen_rtx_COMPLEX ( mode , gen_rtx_REG ( TYPE_MODE ( TYPE_SIZE_UNIT ( mode ) ) , fregno ) , gen_rtx_REG ( TYPE_MODE ( TYPE_SIZE_UNIT ( mode ) ) , fregno + <NUM_LIT> ) ) ;"
GCC,riscv,689,"return riscv_pass_fpr_single (mode, fregno, TYPE_MODE(fields[0].type));"
GCC,riscv,690,}
GCC,riscv,691,}
GCC,riscv,692,
GCC,riscv,693,cfun -> machine -> is_leaf = leaf_function_p ( );
GCC,riscv,694,if (addr.base != NULL) {
GCC,riscv,695,
GCC,riscv,696,
GCC,riscv,697,"split_jump (split_dest, split_src, &jump_dest, &jump_src, CONST_INT (offset));"
GCC,riscv,698,}
GCC,riscv,699,return false ;
GCC,riscv,700,else if ( GET_MODE_BITSIZE ( mode ) == <NUM_LIT> ) {
GCC,riscv,701,
GCC,riscv,702,
GCC,riscv,703,}
GCC,riscv,704,}
GCC,riscv,705,
GCC,riscv,706,
GCC,riscv,707,return emit_insn (gen_pre_dec_insn (this_rtx));
GCC,riscv,708,
GCC,riscv,709,}
GCC,riscv,710,I < n ;
GCC,riscv,711,
GCC,riscv,712,}
GCC,riscv,713,info.cummulative_args = cum;
GCC,riscv,714,
GCC,riscv,715,"return return std::make_pair(mode, std::make_pair(regno1, offset1));"
GCC,riscv,716,
GCC,riscv,717,}
GCC,riscv,718,else return;
GCC,riscv,719,"else output_operand ( op , <NUM_LIT> , file ) ;"
GCC,riscv,720,gcc_unreachable ( ) ;
GCC,riscv,721,
GCC,riscv,722,
GCC,riscv,723,
GCC,riscv,724,
GCC,riscv,725,if (not call_saved) return false;
GCC,riscv,726,
GCC,riscv,727,if (mode == VOIDmode) {
GCC,riscv,728,return_emit <NUM_LIT> }
GCC,riscv,729,gcc_unreachable();
GCC,riscv,730,seqno ++;
GCC,riscv,731,
GCC,riscv,732,
GCC,riscv,733,return temp;
GCC,riscv,734,
GCC,riscv,735,return riscv_operand_byte_rtx ( mode ) != 0 ;
GCC,riscv,736,return n;
GCC,riscv,737,
GCC,riscv,738,arg.registers = 5;
GCC,riscv,739,delta = src mem_offset (mode) ;
GCC,riscv,740,break or H:: break or H::
GCC,riscv,741,switch (GET_CODE (x)) {
GCC,riscv,742,RISCV_STACK_ALIGN ( num_args * UNITS_PER_WORD );
GCC,riscv,743,
GCC,riscv,744,
GCC,riscv,745,}
GCC,riscv,746,}
GCC,riscv,747,
GCC,riscv,748,}
GCC,riscv,749,
GCC,riscv,750,
GCC,riscv,751,
GCC,riscv,752,const char *arg_name = info.name;
GCC,riscv,753,else return (cfun->machine->cpu->pc == &mcount_exec);
GCC,riscv,754,}
GCC,riscv,755,info -> stack_p = (num_words - info -> num_gprs) != 0;
GCC,riscv,756,return false;
GCC,riscv,757,if (MEM_P (x)) {
GCC,riscv,758,"if ( offset != const0_rtx && (targetm.cannot_force_const_mem(mode,src) || can_create_pseudo_p())) {"
GCC,riscv,759,"riscv_emit_move ( dest , src ) ;"
GCC,riscv,760,}
GCC,riscv,761,
GCC,riscv,762,}
GCC,riscv,763,}
GCC,riscv,764,if ( BITS_PER_WORD == <NUM_LIT> ) {
GCC,riscv,765,
GCC,riscv,766,case <NUM_LIT>:
GCC,riscv,767,
GCC,riscv,768,
GCC,riscv,769,
GCC,riscv,770,
GCC,riscv,771,
GCC,riscv,772,"riscv_move_integer (hi, hi, hival) ;"
GCC,riscv,773,"lo = gen_rtx_fmt_ee (CONST_INT, mode, lo, GEN_INT(<NUM_LIT>));"
GCC,riscv,774,return temp ;
GCC,riscv,775,
GCC,riscv,776,n += ( GET_MODE_SIZE ( mode ) + UNITS_PER_WORD - <NUM_LIT> ) / UNITS_PER_WORD ;
GCC,riscv,777,return false ;
GCC,riscv,778,return call_saved && !might_clobber;
GCC,riscv,779,default:
GCC,riscv,780,
GCC,riscv,781,return n;
GCC,riscv,782,
GCC,riscv,783,"reg = riscv_force_temporary (temp, gen_rtx_PLUS (Pmode, offset, reg), FALSE);"
GCC,riscv,784,"loop_reg = copy_addr_to_reg ( XEXP ( mem , <NUM_LIT> ) ) ;"
GCC,riscv,785,}
GCC,riscv,786,}
GCC,riscv,787,
GCC,riscv,788,
GCC,riscv,789,}
GCC,riscv,790,if (riscv_allocate_stack_slots_for_args()) {
GCC,riscv,791,
GCC,riscv,792,}
GCC,riscv,793,
GCC,riscv,794,if (single_insns == double_insns) {
GCC,riscv,795,"riscv_adjust_block_mem( dest, bytes_per_iter, &dest_reg, &dest );"
GCC,riscv,796,}
GCC,riscv,797,}
GCC,riscv,798,
GCC,riscv,799,alt_codes [ alt_cost - <NUM_LIT> ] . value = low_part ;
GCC,riscv,800,RTL_CONST_CALL_P ( insn ) : result = 1 ;
GCC,riscv,801,"emit_insn ( riscv_set_tls_offset_reg ( const0_rtx , sym , a0 ) ) ;"
GCC,riscv,802,likely involve a conditional statement using the result of the function recog_memoized and calling the function get_attr_cannot_copy. It could possibly be something like: if (recog_memoized(insn) >= <NUM_LIT>) {
GCC,riscv,803,if (base == 0) {
GCC,riscv,804,if (plus_one == <NUM_LIT>) {
GCC,riscv,805,
GCC,riscv,806,return true;
GCC,riscv,807,
GCC,riscv,808,
GCC,riscv,809,
GCC,riscv,810,}
GCC,riscv,811,
GCC,riscv,812,
GCC,riscv,813,== NO_REGS) return 0;
GCC,riscv,814,
GCC,riscv,815,"if the condition is met, return true;"
GCC,riscv,816,
GCC,riscv,817,
GCC,riscv,818,fixed_regs[regno] = call_used_regs[regno] = NUM_LIT;
GCC,riscv,819,return x;
GCC,riscv,820,if ( s == bss_section ) return sbss_section ;
GCC,riscv,821,"strcpy ( name , s -> named . name ) ;"
GCC,riscv,822,
GCC,riscv,823,
GCC,riscv,824,
GCC,riscv,825,
GCC,riscv,826,
GCC,riscv,827,
GCC,riscv,828,}
GCC,riscv,829,
GCC,riscv,830,}
GCC,riscv,831,
GCC,riscv,832,
GCC,riscv,833,
GCC,riscv,834,riscv_emit_stack_tie ( ) ;
GCC,riscv,835,
GCC,riscv,836,
GCC,riscv,837,"riscv_emit_int_order_test ( code , zi<NUM_LIT> , target , op0 , op1 ) ;"
GCC,riscv,838,}
GCC,riscv,839,
GCC,riscv,840,}
GCC,riscv,841,"*op0 = gen_rtx_ZERO_EXTEND (word_mode, *op0);"
GCC,riscv,842,
GCC,riscv,843,if (TARGET_ZBB) {
GCC,riscv,844,else if ( ! unsigned_p && GET_MODE ( op ) == HImode ) return COSTS_N_INSNS ( <NUM_LIT> ) }
GCC,riscv,845,
GCC,riscv,846,
GCC,riscv,847,
GCC,riscv,848,
GCC,riscv,849,fields [ <NUM_LIT> ] . offset = offset ;
GCC,riscv,850,
GCC,riscv,851,"return force_reg (mode, code, x, y);"
GCC,riscv,852,
GCC,riscv,853,
GCC,riscv,854,
GCC,riscv,855,
GCC,riscv,856,return arg.name;
GCC,riscv,857,arg_info = info;
GCC,riscv,858,
GCC,riscv,859,
GCC,riscv,860,return false;
GCC,riscv,861,"memcpy(&args, <NUM_LIT>, sizeof args);"
GCC,riscv,862,"return gen_rtx_REG ( mode , fregno + <NUM_LIT> ) ;"
GCC,riscv,863,"return riscv_pass_fpr_scalar ( mode , fregno , TYPE_MODE ( fields [ 0 ] . type ) , fields [ 0 ] . offset ) ;"
GCC,riscv,864,
GCC,riscv,865,}
GCC,riscv,866,"if ( Pmode == SImode ) return gen_got_load_tls_gdti ( dest , sym ) ;"
GCC,riscv,867,
GCC,riscv,868,"return gen_got_load_tls_iegdu (dest, sym);"
GCC,riscv,869,
GCC,riscv,870,return gpr_save_reg_order[(unsigned)REGNO (elt)];
GCC,riscv,871,
GCC,riscv,872,}
GCC,riscv,873,case GTU : return SMALL_OPERAND ( x + <NUM_LIT> + 1 ) ;
GCC,riscv,874,else gcc_unreachable( );
GCC,riscv,875,
GCC,riscv,876,
GCC,riscv,877,
GCC,riscv,878,
GCC,riscv,879,
GCC,riscv,880,return cmp1 == const1_rtx ;
GCC,riscv,881,
GCC,riscv,882,return riscv_align_ok_for_small_data_p ( int_size_in_bytes (TREE_TYPE ( x ) ) );
GCC,riscv,883,
GCC,riscv,884,
GCC,riscv,885,return (riscv_constant_address_p(x) || riscv_stack_pointer_address_p(x) || riscv_control_register_address_p(x));
GCC,riscv,886,
GCC,riscv,887,if ( GET_MODE ( x ) != CCmode && x > 0 ) {
GCC,riscv,888,"if (optimize_function_for_size_p(cfun) && (strcmp(current_pass->name, optimize-size) == 0) && mode == SImode) addr = riscv_optimize_size_lw_offset(base, offset);"
GCC,riscv,889,
GCC,riscv,890,return false;
GCC,riscv,891,"split_const ( src , & base, & offset )"
GCC,riscv,892,
GCC,riscv,893,
GCC,riscv,894,`}
GCC,riscv,895,
GCC,riscv,896,
GCC,riscv,897,default : gcc_unreachable ( ) ;
GCC,riscv,898,}
GCC,riscv,899,
GCC,riscv,900,}
GCC,riscv,901,return combined_attrs;
GCC,riscv,902,
GCC,riscv,903,{
GCC,riscv,904,"else x = riscv_emit_set ( mode , x ) ;"
GCC,riscv,905,
GCC,riscv,906,return new_cost < old_cost;
GCC,riscv,907,if (speed) {
GCC,riscv,908,"an error message printed with the string literal Invalid stack protector guard register: , followed by the value of the string variable riscv_stack_protector_guard_reg_str and an additional string literal explaining the error."
GCC,riscv,909,
GCC,riscv,910,
GCC,riscv,911,
GCC,riscv,912,
GCC,riscv,913,case 4 : return <STR_LIT> ;
GCC,riscv,914,}
GCC,riscv,915,
GCC,riscv,916,
GCC,riscv,917,}
GCC,riscv,918,
GCC,riscv,919,
GCC,riscv,920,
GCC,riscv,921,
GCC,riscv,922,
GCC,riscv,923,}
GCC,riscv,924,return <NUM_LIT> ;
GCC,riscv,925,
GCC,riscv,926,if ( letter && letter != 'z' ) {
GCC,riscv,927,"output_addr_const ( file , riscv_strip_unspec_address ( op ) ) ;"
GCC,riscv,928,
GCC,riscv,929,
GCC,riscv,930,
GCC,riscv,931,
GCC,riscv,932,
GCC,riscv,933,printf(Performing RISC-V reorganization...);
GCC,riscv,934,"The next statement would check the condition: if the 'epilogue_cfa_sp_offset' exists, and the current register number is equal to the HARD_FRAME_POINTER_REGNUM, then it would proceed to create an adjusted call frame address rtx using 'gen_rtx_PLUS' and the stack pointer rtx, with the epilogue_cfa_sp_offset as the immediate value."
GCC,riscv,935,"else if ( rtx_equal_p (count1_rtx, count2_rtx) ) {"
GCC,riscv,936,
GCC,riscv,937,arg.next();
GCC,riscv,938,\N{
GCC,riscv,939,return ++libcall_counter[mask];
GCC,riscv,940,"riscv_emit_move (new_mem, new_reg);"
GCC,riscv,941,"<r> fn ( gen_rtx_REG ( mode , regno ) , mem ) ;"
GCC,riscv,942,
GCC,riscv,943,
GCC,riscv,944,
GCC,riscv,945,
GCC,riscv,946,
GCC,riscv,947,}
GCC,riscv,948,}
GCC,riscv,949,"riscv_emit_move(gen_frame_mem (GET_MODE (address), slot_address) , address);"
GCC,riscv,950,
GCC,riscv,951,}
GCC,riscv,952,return true;
GCC,riscv,953,<return;
GCC,riscv,954,
GCC,riscv,955,"low_src = riscv_subword ( src , false ) ;"
GCC,riscv,956,}
GCC,riscv,957,
GCC,riscv,958,"return gen_rtx_fmt_ee ( PLUS , mode , hi , lo ) ;"
GCC,riscv,959,
GCC,riscv,960,
GCC,riscv,961,rtx label;
GCC,riscv,962,seqno ++ ;
GCC,riscv,963,
GCC,riscv,964,}
GCC,riscv,965,
GCC,riscv,966,"if ( CONST_P ( op ) ) return simplify_gen_subreg ( word_mode , op , mode , byte ) ;"
GCC,riscv,967,if (mode == VOIDmode ) return mode ;
GCC,riscv,968,
GCC,riscv,969,return inst;
GCC,riscv,970,
GCC,riscv,971,
GCC,riscv,972,"else: return gen_tls_add_tp_dedi (dest, base, tp, sym)."
GCC,riscv,973,"else if ( Pmode == QImode ) return gen_tls_add_tp_qedi ( dest , base , tp , sym ) ;"
GCC,riscv,974,"mem = adjust_address (m_tramp, SImode, <NUM_LIT> * GET_MODE_SIZE(SImode) + <NUM_LIT>) ;"
GCC,riscv,975,
GCC,riscv,976,'}
GCC,riscv,977,
GCC,riscv,978,"elif (offset != NULL) base = gen_rtx_PLUS (Pmode, base , offset) ;"
GCC,riscv,979,"return (symbol_type == RISCV_SYMBOL_TYPE_PCREL) ? gen_riscv_pcrel_addr (base, offset) : gen_riscv_relaxed_addr (base, offset);"
GCC,riscv,980,return temp;
GCC,riscv,981,return frame -> save_libcall_adjustment != <NUM_LIT> ;
GCC,riscv,982,
GCC,riscv,983,
GCC,riscv,984,return offset == <NUM_LIT> ;
GCC,riscv,985,rtx offset ;
GCC,riscv,986,return false;
GCC,riscv,987,}
GCC,riscv,988,if (decl is not a riscv naked function) {
GCC,riscv,989,if ( cmp1 == const0_rtx ) return(cmp0);
GCC,riscv,990,else if ( cmp1 == const0_rtx ) return cmp1 ;
GCC,riscv,991,break ;
GCC,riscv,992,
GCC,riscv,993,
GCC,riscv,994,"* base = XEXP ( addr , <NUM_LIT> ) ;"
GCC,riscv,995,<x = ptr;
GCC,riscv,996,return false;
GCC,riscv,997,
GCC,riscv,998,
GCC,riscv,999,
GCC,riscv,1000,}
GCC,riscv,1001,
GCC,riscv,1002,gcc_assert ( MEM_P ( base1 ) ) ;
GCC,riscv,1003,
GCC,riscv,1004,"operands[reg_op] = gen_rtx_REG(mode, regno3);"
GCC,riscv,1005,"operands [reg_op] = gen_rtx_MEM (mode, plus_constant (mode, stack_pointer_rtx, offset));"
GCC,riscv,1006,
GCC,riscv,1007,"insn = emit_insn( gen_rtx_PARALLEL( VOIDmode, gen_rtvec( <NUM_LIT>, set1, set2 ) ) ) ;"
GCC,riscv,1008,if (load_p) {
GCC,arc,0,builtin_define ( <STR_LIT> ) ;
GCC,arc,1,"builtin_assert ( pfile, NAME, CONDITION ) ;"
GCC,arc,2,
GCC,arc,3,invoke_builtin_func();
GCC,arc,4,if ( TARGET_BIG_ENDIAN ) builtin_define ( <STR_LIT> ) ;
GCC,arc,5,builtin_define ( TARGET_BIG_ENDIAN ? <STR_LIT> : <STR_LIT> ) ;
GCC,arc,6,"Quote or print out the statement cpp_define ( pfile , name ) ;"
GCC,arc,7,"if (!def_p) cpp_undef (pfile, name);"
GCC,arc,8,default: break;
GCC,arc,9,
GCC,arc,10,}
GCC,arc,11,
GCC,arc,12,return true;
GCC,arc,13,}
GCC,arc,14,int intval2 = ( REG_P ( operands [ 4 ] ) ? 1 : CONST_INT_P ( operands [ 5] ) ? INTVAL ( operands [ 6] ) : 7 ) ;
GCC,arc,15,"reg = gen_rtx_REG ( SImode , end_reg - <NUM_LIT> ) ;"
GCC,arc,16,
GCC,arc,17,
GCC,arc,18,
GCC,arc,19,
GCC,arc,20,switch (GET_CODE (xop[default] + i)) {
GCC,arc,21,
GCC,arc,22,"operands[<NUM_LIT>] =  gen_rtx_PLUS (SImode, operands[<NUM_LIT>], operands[<NUM_LIT>]);"
GCC,arc,23,
GCC,arc,24,"operands[<NUM_LIT>] = gen_rtx_MINUS ( SImode , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] );"
GCC,arc,25,}
GCC,arc,26,"if ( arc_hazard ( insn , succ1 ) || arc_check_release31a ( insn , succ1 ) ) emit_insn_before ( gen_nopv ( ) , succ1 ) ;"
GCC,arc,27,}
GCC,arc,28,}
GCC,arc,29,arc_ccfsm_state += <NUM_LIT> ;
GCC,arc,30,}
GCC,arc,31,if ( ! current_frame_info . initialized ) return <NUM_LIT> ;
GCC,arc,32,if ( current_frame_info.total_size == <NUM_LIT> ) return <NUM_LIT> ;
GCC,arc,33,
GCC,arc,34,
GCC,arc,35,arc_punct_chars [ '.' ] = <NUM_LIT> ;
GCC,arc,36,}
GCC,arc,37,case CONST_INT : return SMALL_INT ( plus1 ) ? <NUM_LIT> : <NUM_LIT> ;
GCC,arc,38,"fputs(<STR_LIT>, asm_out_file);"
GCC,arc,39,
GCC,arc,40,
GCC,arc,41,
GCC,arc,42,
GCC,arc,43,
GCC,arc,44,
GCC,arc,45,if ( fn_type == ARC_FUNCTION_NORMAL && a == NULL ) {
GCC,arc,46,if (current_frame_info.total_size == <NUM_LIT>) return <NUM_LIT>;
GCC,arc,47,
GCC,arc,48,return <NUM_LIT>;
GCC,arc,49,"fprintf ( FILE , <STR_LIT> , XSTR ( SYMREF , <NUM_LIT> ) , XSTR ( SYMREF , <NUM_LIT> ) , arc_mangle_suffix ) ;"
GCC,arc,50,
GCC,arc,51,
GCC,arc,52,
GCC,arc,53,"Case OPT_mcpu_ : return strcmp ( arg , <STR_LIT> ) == <NUM_LIT> || ARC_EXTENSION_CPU ( arg ) ;"
GCC,arc,54,arc_punct_chars [ '@' ] = <NUM_LIT> ;
GCC,arc,55,
GCC,arc,56,
GCC,arc,57,
GCC,arc,58,
GCC,arc,59,"printf(%slabel%lu\n, prefix, labelno+1);"
GCC,arc,60,}
GCC,arc,61,fclose(file);
GCC,arc,62,break ;
GCC,arc,63,) ) {
GCC,arc,64,return false ;
GCC,arc,65,
GCC,arc,66,}
GCC,arc,67,{
GCC,arc,68,
GCC,arc,69,
GCC,arc,70,}
GCC,arc,71,"There are three possible outcomes: a symbolic_operand, a CONST_INT if it is a legitimate constant, or a REG."
GCC,arc,72,f = const0_rtx }
GCC,arc,73,"return get_mem_operand(op, mode);"
GCC,arc,74,
GCC,arc,75,
GCC,arc,76,return 0 ;
GCC,arc,77,"emjit_insn (gen_rtx_IF (VOIDmode , gen_rtix_COMPARE (mode, x, y), cc_reg));"
GCC,arc,78,<NUM_LIT> }
GCC,arc,79,break;
GCC,arc,80,
GCC,arc,81,default: return <NUM_LIT>;
GCC,arc,82,}
GCC,arc,83,return <NUM_LIT_2> ;
GCC,arc,84,break;
GCC,arc,85,
GCC,arc,86,
GCC,arc,87,
GCC,arc,88,
GCC,arc,89,"return force_nonimmediate_operand(op, mode);"
GCC,arc,90,
GCC,arc,91,"if ( GET_MODE ( XEXP ( op , <NUM_LIT> ) ) == CCNOmode ) return ( code == LTU || code == GEU || code == GTU || code == LEU ) ;"
GCC,arc,92,case COND_SET_V :
GCC,arc,93,break ;
GCC,arc,94,
GCC,arc,95,"op = XEXP (op, <STR_LIT>);"
GCC,arc,96,
GCC,arc,97,
GCC,arc,98,"op = XEXP ( op , <ADDR_EXPR> ) ;"
GCC,arc,99,
GCC,arc,100,}
GCC,arc,101,return <NUM_LIT>;
GCC,arc,102,
GCC,arc,103,
GCC,arc,104,after this would be return bytes;
GCC,arc,105,int ret = arg_num * 2;
GCC,arc,106,"ASM_OUTPUT_VALUE ( stream , name , <NUM_LIT> , <NUM_LIT> ) ;"
GCC,arc,107,"( * targetm . asm_out . assemble_visibility ) ( stream , lv , vis ) ;"
GCC,arc,108,
GCC,arc,109,
GCC,arc,110,
GCC,arc,111,
GCC,arc,112,}
GCC,arc,113,frame_info -> gmask = gmask;
GCC,arc,114,fn_type = ARC_FUNCTION_ILINK3;
GCC,arc,115,return fun -> machine -> fn_type = fn_type ;
GCC,arc,116,return <NUM_LIT> ;
GCC,arc,117,}
GCC,arc,118,return decl;
GCC,arc,119,
GCC,arc,120,
GCC,arc,121,
GCC,arc,122,}
GCC,arc,123,epilogue_done:.
GCC,arc,124,If (store[i ^2] ) then emit_insn(store[i ^2]);
GCC,arc,125,likely involve the return false;
GCC,arc,126,"frame_pointer_rtx = gen_frame_mem ( Pmode , gen_rtx_PRE_DEC ( Pmode , stack_pointer_rtx ) ) ;"
GCC,arc,127,"pat = gen_rtx_NOTE ( Pmode , gen_rtx_SYMBOL_REF ( Pmode , <STR_LIT> ) , pat ) ;"
GCC,arc,128,
GCC,arc,129,
GCC,arc,130,
GCC,arc,131,
GCC,arc,132,}
GCC,arc,133,execute the `* cum = ARC_NEXT_ARG_REG ( * cum ) ;
GCC,arc,134,i = 0 ;
GCC,arc,135,
GCC,arc,136,}
GCC,arc,137,
GCC,arc,138,
GCC,arc,139,}
GCC,arc,140,"return arc600_corereg_hazard ( pred , succ ) ;"
GCC,arc,141,if ( JUMP_P ( insn ) ) {
GCC,arc,142,
GCC,arc,143,
GCC,arc,144,if ( ( from == ARG_POINTER_REGNUM ) && ( to == FRAME_POINTER_REGNUM ) ) {
GCC,arc,145,
GCC,arc,146,
GCC,arc,147,
GCC,arc,148,machine->insn_align = -1;
GCC,arc,149,else arc_mode_class [ i ] = <NUM_LIT> << ( int ) SF_MODE ;
GCC,arc,150,}
GCC,arc,151,
GCC,arc,152,
GCC,arc,153,if ( INSN_P ( prev ) && recog_memoized ( prev ) >= <NUM_LIT-1> ) return <NUM_LIT-1>;
GCC,arc,154,
GCC,arc,155,
GCC,arc,156,return false;
GCC,arc,157,
GCC,arc,158,
GCC,arc,159,
GCC,arc,160,"inner = force_operand (inner , NULL_RTX, VOIDmode) ;"
GCC,arc,161,"emit_move_insn ( pat , addr ) ;"
GCC,arc,162,
GCC,arc,163,
GCC,arc,164,
GCC,arc,165,}
GCC,arc,166,return false;
GCC,arc,167,return false ;
GCC,arc,168,
GCC,arc,169,pat = PATTERN ( insn ) ;
GCC,arc,170,
GCC,arc,171,
GCC,arc,172,"printf ( Image file name %s saved to buffer %s. , fname, buf ) ;"
GCC,arc,173,}
GCC,arc,174,"arc_output_pic_addr_const (file, XVECEXP(x, <NUM_LIT>, <NUM_LIT>), code);"
GCC,arc,175,break ;
GCC,arc,176,
GCC,arc,177,prev->set_note (NOTE_INSN_DELETED);
GCC,arc,178,
GCC,arc,179,case SYMBOL_REF: {
GCC,arc,180,
GCC,arc,181,}
GCC,arc,182,continue;
GCC,arc,183,
GCC,arc,184,
GCC,arc,185,
GCC,arc,186,
GCC,arc,187,}
GCC,arc,188,
GCC,arc,189,print(The code of x is PLUS.);
GCC,arc,190,}
GCC,arc,191,"addr = plus_constant ( Pmode , base_reg , offset ) ;"
GCC,arc,192,addr = Pmode ;
GCC,arc,193,return CC_Cmode;
GCC,arc,194,next_cum = * get_cumulative_args ( args_so_far ) ;
GCC,arc,195,
GCC,arc,196,}
GCC,arc,197,"emit_insn ( gen_rtx_SET ( VOIDmode , operands [ NUM_LIT ] , operands [ NUM_LIT ] ) ) ;"
GCC,arc,198,
GCC,arc,199,
GCC,arc,200,{
GCC,arc,201,
GCC,arc,202,}
GCC,arc,203,"return XEXP ( pat , 0 ) ;"
GCC,arc,204,"if ( XEXP ( dest , <NUM_LIT> ) == pc_rtx ) dest_uid = <NUM_LIT> ;"
GCC,arc,205,case constx : return VALID ;
GCC,arc,206,default : }
GCC,arc,207,break;
GCC,arc,208,if (mode != VOIDmode) {
GCC,arc,209,size = GET_MODE_SIZE ( mode ) ;
GCC,arc,210,rarr = gen_rtx_FRAME ( insn ) ;
GCC,arc,211,return temp;
GCC,arc,212,if (GET_CODE(operands[<NUM_LIT>]) != MEM) {
GCC,arc,213,block[offset] = value;
GCC,arc,214,"evaluating the else if clause: if ( reuse ) emit_insn ( gen_add2_insn ( addr , offs ) )."
GCC,arc,215,
GCC,arc,216,
GCC,arc,217,}
GCC,arc,218,gcc_unreachable();
GCC,arc,219,}
GCC,arc,220,
GCC,arc,221,ctxt->gimple_optimization_pending();
GCC,arc,222,"pat = arc_legitimize_address_0 ( pat , pat , mode ) ;"
GCC,arc,223,operands [ <NUM_LIT> ] = pat ;
GCC,arc,224,else return false;
GCC,arc,225,
GCC,arc,226,
GCC,arc,227,
GCC,arc,228,
GCC,arc,229,
GCC,arc,230,
GCC,arc,231,"else * srcp = XVECEXP ( * slot , <NUM_LIT> , <NUM_LIT> );"
GCC,arc,232,
GCC,arc,233,
GCC,arc,234,
GCC,arc,235,}
GCC,arc,236,gcc_assert ( cfun -> machine -> insns_ra_save == 0 || size_to_deallocate + cfun -> machine -> insns_ra_save == UNITS_PER_WORD || cfun -> machine -> insns_ra_save == - 1 ) ;
GCC,arc,237,
GCC,arc,238,<NUM_LIT> ;
GCC,arc,239,"pat = gen_rtx_PLUS (Pmode, pat, gen_rtx_SYMBOL_REF (Pmode, <STR_LIT>)) ;"
GCC,arc,240,
GCC,arc,241,}
GCC,arc,242,
GCC,arc,243,case <NUM_LIT> : {
GCC,arc,244,case <NUM_LIT>: if (!NONDEBUG_INSN_P(insn)) break;
GCC,arc,245,
GCC,arc,246,arc_mode_class [ i ] = <NUM_LIT> << ( int ) C_MODE ;
GCC,arc,247,}
GCC,arc,248,if ( optimize_size == <NUM_LIT> ) optimize_flag = <NUM_LIT> ;
GCC,arc,249,
GCC,arc,250,"output_addr_const(file, addr);"
GCC,arc,251,"emit_insn ( gen_rtx_SET ( srcHigh , gen_rtx_UNSPEC_VOLATILE (Pmode, gen_rtvec(3,dest), VUNSPEC_ARC_LR_HIGH ))) ;"
GCC,arc,252,else {
GCC,arc,253,}
GCC,arc,254,
GCC,arc,255,
GCC,arc,256,static void emit_unlikely_jump ( rtx insn ) {
GCC,arc,257,if (TARGET_HARD_FLOAT && ((cmode == SFmode && TARGET_FP_SP_BASE) || (cmode == DFmode && TARGET_FP_DP_BASE))) {
GCC,arc,258,return true;
GCC,arc,259,emit_insn ( pat ) ;
GCC,arc,260,"rtx set = gen_rtx_SET ( mode , operands [ <NUM_LIT> ] , pat ) ;"
GCC,arc,261,}
GCC,arc,262,"if ( arc_hazard ( insn , succ1 ) ) {"
GCC,arc,263,"if ( GET_CODE ( plus1 ) != REG && ( GET_CODE ( plus1 ) != MULT || ! CONST_INT_P ( XEXP ( plus1 , <NUM_LIT> ) ) || ( INTVAL ( XEXP ( plus1 , <NUM_LIT> ) ) != <NUM_LIT> && INTVAL ( XEXP ( plus1 , <NUM_LIT> ) ) != <NUM_LIT> ) ) ) break ;"
GCC,arc,264,"else if ( GET_CODE ( SET_SRC ( body ) , <NUM_LIT> ) == SIMPLE_RETURN ) {"
GCC,arc,265,(}
GCC,arc,266,RTL_PURE_CALL_P (call_insn) = <NUM_LIT>;
GCC,arc,267,emit_insn (pat);
GCC,arc,268,"pat = gen_rtx_IF_THEN_ELSE (gen_rtx_COMPARE (PATTERN (pat), PATTERN (ARC_UNSPEC_OFFSET)), substitute (pat, PATTERN (pat)),pat );"
GCC,arc,269,}
GCC,arc,270,
GCC,arc,271,pass_register ( &arc_ifcvt4_info ) ;
GCC,arc,272,register_pass(&arc_ifcvt5_info);
GCC,arc,273,
GCC,arc,274,break;
GCC,arc,275,
GCC,arc,276,return true ;
GCC,arc,277,return true ;
GCC,arc,278,}
GCC,arc,279,"x = XEXP ( x , <NUM_LIT> ) ;"
GCC,arc,280,return true ;
GCC,arc,281,}
GCC,arc,282,
GCC,arc,283,
GCC,arc,284,}
GCC,arc,285,return orig;
GCC,arc,286,
GCC,arc,287,}
GCC,arc,288,
GCC,arc,289,
GCC,arc,290,
GCC,arc,291,else pat = <STR_LIT> ;
GCC,arc,292,
GCC,arc,293,break ;
GCC,arc,294,
GCC,arc,295,"arc_output_pic_addr_const ( file , c , <NUM_LIT> ) ;"
GCC,arc,296,"rtx srcLow = simplify_gen_subreg (SImode, src, DFmode, TARGET_BIG_ENDIAN ? <NUM_LIT> : <NUM_LIT>);"
GCC,arc,297,return <NUM_LIT> ;
GCC,arc,298,return false ;
GCC,arc,299,}
GCC,arc,300,"* total += ( rtx_cost ( XEXP ( x , <NUM_LIT> ) , mode , MINUS , <NUM_LIT> , speed ) + rtx_cost ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) , mode , <NUM_LIT> , speed ) ) ;"
GCC,arc,301,
GCC,arc,302,return true ;
GCC,arc,303,case V8SImode : return TARGET_SIMD_SET ;
GCC,arc,304,return;
GCC,arc,305,if (jump) {
GCC,arc,306,operands [ <NUM_LIT> ] = pat ;
GCC,arc,307,operands [<NUM_LIT>] = temp;
GCC,arc,308,
GCC,arc,309,sizes->quick_push(<NUM_LIT>);
GCC,arc,310,
GCC,arc,311,
GCC,arc,312,
GCC,arc,313,
GCC,arc,314,}
GCC,arc,315,
GCC,arc,316,
GCC,arc,317,illegal instruction ;
GCC,arc,318,
GCC,arc,319,
GCC,arc,320,return;
GCC,arc,321,"tmpx [ i ] = adjust_address_nv ( operands [ <NUM_LIT> ] , GET_MODE ( operands [ <NUM_LIT> ] ) , dst_addr ) if ( n_pieces < ( unsigned int ) <NUM_LIT> ) {"
GCC,arc,322,store [ <NUM_LIT> ] = store [ <NUM_LIT> ] = NULL_RTX ;
GCC,arc,323,"asm_fprintf ( asm_out_file , <STR_LIT> , TARGET_RF16 ? <NUM_LIT> : <NUM_LIT> ) ;"
GCC,arc,324,"asm_fprintf ( asm_out_file , <STR_LIT> , ( disk_fs != - <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ) ;"
GCC,arc,325,
GCC,arc,326,
GCC,arc,327,
GCC,arc,328,if ( from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM ) {
GCC,arc,329,if ( from != ARG_POINTER_REGNUM || to != STACK_POINTER_REGNUM ) {
GCC,arc,330,return false;
GCC,arc,331,
GCC,arc,332,}
GCC,arc,333,else return false;
GCC,arc,59,
GCC,arc,334,
GCC,arc,335,break ;
GCC,arc,336,then {
GCC,arc,337,}
GCC,arc,338,}
GCC,arc,339,if ( ( ( fn_type & ARC_FUNCTION_ILINK1 ) | ARC_FUNCTION_FIRQ ) != <NUM_LIT> ) regno = ILINK2_REGNUM ;
GCC,arc,340,
GCC,arc,341,
GCC,arc,342,if (addr && !REG_P(x) && MEM_P(x)) {
GCC,arc,343,if ( machine -> force_short_prefix >= <NUM_LIT> ) return machine -> force_short_prefix ;
GCC,arc,344,if (check_attr > <NUM_LIT>) {
GCC,arc,345,return mask & (align % mask) == <NUM_LIT> ;
GCC,arc,346,< returns const_rtx x = * iter ;
GCC,arc,347,case ORDERED : return ARC_CC_NC ;
GCC,arc,348,
GCC,arc,349,
GCC,arc,350,return ;
GCC,arc,351,}
GCC,arc,352,
GCC,arc,353,}
GCC,arc,354,
GCC,arc,355,rtx next_statement;
GCC,arc,356,
GCC,arc,357,gcc_assert ( total_size == ARC_STACK_ALIGN ( total_size ) ) ;
GCC,arc,358,arc_regno_reg_class[ICC_REG] = NO_REGS;
GCC,arc,359,for (regno = ENTER_LEAVE_START_REG + 1;
GCC,arc,360,
GCC,arc,361,}
GCC,arc,362,}
GCC,arc,363,
GCC,arc,364,
GCC,arc,365,arc_init_reg_tables();
GCC,arc,366,
GCC,arc,367,else return false ;
GCC,arc,368,return false;
GCC,arc,369,
GCC,arc,370,}
GCC,arc,371,
GCC,arc,372,"frame_deallocated += frame_restore_reg(reg, offs);"
GCC,arc,373,
GCC,arc,374,
GCC,arc,375,
GCC,arc,376,}
GCC,arc,377,}
GCC,arc,378,if ( alpha_prologue_desp == <NUM_LIT> ) {
GCC,arc,379,if ( gmask ) for ( int i = <NUM_LIT> ;
GCC,arc,380,}
GCC,arc,381,
GCC,arc,382,return false;
GCC,arc,383,return false ;
GCC,arc,384,}
GCC,arc,385,if ( pat ) {
GCC,arc,386,return GEN_FCN ( icode ) ( arg [ <NUM_LIT> ] ) ;
GCC,arc,387,
GCC,arc,388,}
GCC,arc,389,
GCC,arc,390,break;
GCC,arc,391,return new_section;
GCC,arc,392,new_section->next = sec;
GCC,arc,393,
GCC,arc,394,
GCC,arc,395,
GCC,arc,396,
GCC,arc,397,
GCC,arc,398,
GCC,arc,399,"<j> = arc_asm_insn_p ( XVECEXP ( x , <NUM_LIT> , i - 1 ) ) ;"
GCC,arc,400,"if ( size == <NUM_LIT> ) ASM_OUTPUT_SKIP ( stream , <NUM_LIT> ) ;"
GCC,arc,401,"asm_fprintf ( f , <STR_LIT> , reg_names [ STATIC_CHAIN_REGNUM ] ) ;"
GCC,arc,402,"asm_fprintf ( f , <STR_LIT> , ARC_ARG_POINTER_REG ) ;"
GCC,arc,403,
GCC,arc,404,
GCC,arc,405,
GCC,arc,406,;
GCC,arc,407,return arg;
GCC,arc,408,CALL_INSN_FUNCTION_USAGE ( insn ) = {
GCC,arc,409,
GCC,arc,410,return false;
GCC,arc,411,
GCC,arc,412,
GCC,arc,413,
GCC,arc,414,if (var > 5 || var2) return false ;
GCC,arc,415,{
GCC,arc,416,
GCC,arc,417,
GCC,arc,418,}
GCC,arc,419,closing curly bracket (}
GCC,arc,420,
GCC,arc,421,end if;
GCC,arc,422,
GCC,arc,423,
GCC,arc,424,
GCC,arc,425,
GCC,arc,426,return false;
GCC,arc,427,
GCC,arc,428,if ( ! IS_POWEROF2_P ( ival + <NUM_LIT> ) ) return false ;
GCC,arc,429,
GCC,arc,430,}
GCC,arc,431,}
GCC,arc,432,}
GCC,arc,433,"if ( arc_compute_millicode_save_restore_regs ( gmask , frame_info ) ) frame_info -> save_return_addr = true ;"
GCC,arc,434,
GCC,arc,435,gcc_unreachable ( ) ;
GCC,arc,436,if ( regno == <NUM_LIT> ) {
GCC,arc,437,return <NUM_LIT>;
GCC,arc,438,if ((l1 || l2) && (m1 || m2) && (s1 || s2)) {
GCC,arc,439,
GCC,arc,440,if ( MEM_P (x) ) return x ;
GCC,arc,441,return x;
GCC,arc,442,"The next statement could potentially be a conditional statement or a return statement, depending on the values of t1 and t2. If t1 and t2 have values, the statement could be return gen_rtx_PLUS (GET_MODE (op), t1, t2);"
GCC,arc,443,
GCC,arc,444,
GCC,arc,445,offset = UNITS_PER_WORD * ( irq_ctrl_saved . irq_save_last_reg + <NUM_LIT> + irq_ctrl_saved . irq_save_blink + irq_ctrl_saved . irq_save_lpcount ) ;
GCC,arc,446,
GCC,arc,447,
GCC,arc,448,
GCC,arc,449,
GCC,arc,450,"rtx symbol = XEXP ( rtl , <NUM_LIT> ) ;"
GCC,arc,451,
GCC,arc,452,regno > gmask && regno >= ENTER_LEAVE_END_REG ;
GCC,arc,453,
GCC,arc,454,
GCC,arc,455,
GCC,arc,456,
GCC,arc,457,"emit_insn ( gen_rtx_SET ( out , gen_rtx_AND ( SImode , gen_lowpart_common ( SImode , newval ) , mask ) ) ) ;"
GCC,arc,458,
GCC,arc,459,"asm_fprintf(asm_out_file, <STR_LIT>, TARGET_OPTFPE ? <NUM_LIT> : <NUM_LIT>) ;"
GCC,arc,460,if (arc_tp_regno != -4) {
GCC,arc,461,
GCC,arc,462,arc_ccfsm_current.INSN_ADDRESSES ( INSN_UID (insn) );
GCC,arc,463,
GCC,arc,464,}
GCC,arc,465,
GCC,arc,466,}
GCC,arc,467,
GCC,arc,468,"return gen_rtx_REG ( mode , <NUM_LIT> ) ;"
GCC,arc,469,
GCC,arc,470,
GCC,arc,471,"assert (GET_CODE ( XEXP ( cond , <NUM_LIT> ) ) == code);"
GCC,arc,472,"tree attrs = tree_cons ( get_identifier ( <STR_LIT> ) , NULL_TREE , TYPE_ATTRIBUTES ( fntype ) ) ;"
GCC,arc,473,TREE_TYPE(*node) = fntype;
GCC,arc,474,* no_add_attrs = false ;
GCC,arc,475,
GCC,arc,476,* no_add_attrs = true ;
GCC,arc,477,}
GCC,arc,478,if ( regno < FIRST_PSEUDO_REGISTER &amp;
GCC,arc,479,
GCC,arc,480,
GCC,arc,481,gcc_unreachable ();
GCC,arc,482,
GCC,arc,483,
GCC,arc,484,"emit_insn (gen_label_ref ( fndecl , GET_MODE (fnaddr))) ;"
GCC,arc,485,
GCC,arc,486,arc_init_timer();
GCC,arc,487,}
GCC,arc,488,arc_mode_class [ i ] = ( <NUM_LIT> << ( int ) V_MODE ) ;
GCC,arc,489,if (type == NONE) {
GCC,arc,490,}
GCC,arc,491,
GCC,arc,492,
GCC,arc,493,
GCC,arc,494,return false;
GCC,arc,495,
GCC,arc,496,
GCC,arc,497,
GCC,arc,498,return TARGET_JLI_ALWAYS ;
GCC,arc,499,
GCC,arc,500,
GCC,arc,501,"if ( lookup_attribute ( STR_LIT, attrs ) ) return true;"
GCC,arc,502,if ( !attrs) return false;
GCC,arc,503,
GCC,arc,504,}
GCC,arc,505,
GCC,arc,506,
GCC,arc,507,
GCC,arc,508,
GCC,arc,509,case E_<MODE>: return <MODE_STATEMENT> ;
GCC,arc,510,
GCC,arc,511,return orig_x;
GCC,arc,512,
GCC,arc,513,}
GCC,arc,514,{
GCC,arc,515,
GCC,arc,516,
GCC,arc,517,
GCC,arc,518,"return gen_rtx_PLUS ( Pmode , gen_rtx_REG ( Pmode , arc_tp_regno ) , addr ) ;"
GCC,arc,519,
GCC,arc,520,
GCC,arc,521,a '}
GCC,arc,522,a return statement with a boolean value indicating whether the conditions are met. For example: return true;
GCC,arc,523,
GCC,arc,524,
GCC,arc,525,if (GET_CODE (PATTERN (INSN)) == ADDR_DIFF) {
GCC,arc,526,
GCC,arc,527,
GCC,arc,528,ret = 0;
GCC,arc,529,int sum = intval + neg_intval ;
GCC,arc,530,}
GCC,arc,531,return buf;
GCC,arc,532,
GCC,arc,533,
GCC,arc,534,
GCC,arc,535,if (model == RELEASE) {
GCC,arc,536,}
GCC,arc,537,pat = PATTERN (dlay);
GCC,arc,538,
GCC,arc,539,
GCC,arc,540,}
GCC,arc,541,"if ( need_atomic_barrier_p ( model , true ) ) emit_insn ( gen_thread_fence ( ) ) ;"
GCC,arc,542,
GCC,arc,543,}
GCC,arc,544,}
GCC,arc,545,
GCC,arc,546,
GCC,arc,547,
GCC,arc,548,If (get_code(op) == LT || get_code(op) == LE ) {
GCC,arc,549,
GCC,arc,550,
GCC,arc,551,
GCC,arc,552,
GCC,arc,553,gcc_assert ( regno != <NUM_LIT2> ) ;
GCC,arc,554,
GCC,arc,555,return count + 1;
GCC,arc,556,"likely check if the variable size is equal to or greater than either <NUM_LIT> or <NUM_LIT>, depending on the value of size and the boolean expression ( TARGET_V2 ? <NUM_LIT> : <NUM_LIT> )."
GCC,arc,557,"XVECEXP ( insn , <NUM_LIT> , indx ) = gen_rtx_CAND (  , <NUM_LIT> ) ;"
GCC,arc,558,reg = GEN_INT ( <NUM_LIT> ) ;
GCC,arc,559,If (gmask & (1 << (i - 1))) == 1 then save_mode = DImode;
GCC,arc,560,
GCC,arc,561,}
GCC,arc,562,return priority + <NUM_STRING> ;
GCC,arc,563,else {
GCC,arc,564,break ;
GCC,arc,565,sri->icode = in_p ? CODE_FOR_reload_sy_load : CODE_FOR_reload_sy_store;
GCC,arc,566,if (store_p) {
GCC,arc,567,"if (!store_p) emit_insn (gen_rtx_SET (mem, reg)) ;"
GCC,arc,568,return CC_GTmode ;
GCC,arc,569,
GCC,arc,570,}
GCC,arc,571,
GCC,arc,572,if (is_short) {
GCC,arc,573,return l_tmpl;
GCC,arc,574,
GCC,arc,575,
GCC,arc,576,if (mod_f == MEMMODEL_RELAXED) {
GCC,arc,577,maskx = 8 << (__builtin_ffs(mask) - 8);
GCC,arc,578,
GCC,arc,579,
GCC,arc,580,out_addr = SUBREG_REG(out_addr);
GCC,arc,581,
GCC,arc,582,return false;
GCC,arc,583,assert (x != NULL);
GCC,arc,584,
GCC,arc,585,
GCC,arc,586,`s}
GCC,arc,587,
GCC,arc,588,
GCC,arc,589,
GCC,arc,590,
GCC,arc,591,: The code
GCC,arc,592,
GCC,arc,593,
GCC,arc,594,"return default_use_by_pieces_infrastructure_p ( size , align , op , speed_p ) ;"
GCC,arc,595,case E_V16QImode : return TARGET_SIMD_SET ;
GCC,arc,596,default: return TARGET_PLUS_DMPY;
GCC,arc,597,return get_attr_length ( insn ) & <NUM_LIT> ;
GCC,arc,598,
GCC,arc,599,case SET: return x;
GCC,arc,600,"else if ( GET_CODE ( dest ) == AND ) dest = XEXP ( dest , XEXP ( dest , <NUM_LIT> ) && pc_rtx ? <NUM_LIT> : <NUM_LIT> ) ;"
GCC,arc,601,"if (GET_CODE(dest) == LABEL) dest = SET_SRC(XVECEXP(dest, <NUM_LIT>, <NUM_LIT>));"
GCC,arc,602,}
GCC,arc,603,
GCC,arc,604,if (align != <NUM_LIT>) {
GCC,arc,605,
GCC,arc,606,
GCC,arc,607,probably the opening curly bracket {
GCC,arc,608,
GCC,arc,609,
GCC,arc,610,
GCC,arc,611,
GCC,arc,612,
GCC,arc,613,
GCC,arc,614,
GCC,arc,615,
GCC,arc,616,
GCC,arc,617,
GCC,arc,618,RTX_FRAME_RELATED_P ( x ) = <NUM_LIT> ;
GCC,arc,619,
GCC,arc,620,"add_reg_note ( insn , REG_INC , reg ) ;"
GCC,arc,621,
GCC,arc,622,"add_reg_note(insn, REG_CFA_DEF_CFA, plus_constant(Pmode, stack_pointer_rtx, GET_MODE_SIZE(GET_MODE(reg)) + offset));"
GCC,arc,623,
GCC,arc,624,return addr;
GCC,arc,625,
GCC,arc,626,return frame_stack + offset ;
GCC,arc,627,}
GCC,arc,628,
GCC,arc,629,return acc1;
GCC,arc,630,
GCC,arc,631,}
GCC,arc,632,
GCC,arc,633,if ( REGNO ( base ) == cur_base ) return false;
GCC,arc,634,}
GCC,arc,635,align =  DECL_ALIGN ( decl ) ;
GCC,arc,636,"return get_symbol_alignment ( XEXP ( x , <NUM_LIT> ) ) ;"
GCC,arc,637,
GCC,arc,638,if ( entry_after -> rtx_next ) {
GCC,arc,639,
GCC,arc,640,
GCC,arc,641,case <NUM_LIT> : lpcount = <NUM_LIT> ;
GCC,arc,642,}
GCC,arc,643,insn = get_insns() ;
GCC,arc,644,pat = SET_SRC(pat);
GCC,arc,645,return true;
GCC,arc,646,
GCC,arc,647,return new arc_ifcvt_pass(ctxt);
GCC,arc,648,}
GCC,arc,649,return false;
GCC,arc,650,(}
GCC,arc,651,
GCC,arc,652,
GCC,arc,653,return true;
GCC,arc,654,(}
GCC,arc,655,"instruction insn_next = NEXT_INSN ( insn,9,1 );"
GCC,arc,656,return;
GCC,arc,657,
GCC,arc,658,return <NUM_LIT> ;
GCC,arc,659,"return LIM_CALLS (PASS_ARC_IFCVT, ctxt);"
GCC,arc,660,
GCC,arc,661,
GCC,arc,662,std::cout << Predicate delay successfully performed on ARCompact instructions. << std::endl;
GCC,arc,663,return insn;
GCC,arc,664,operands[<NUM_LIT>] = tmp;
GCC,arc,665,}
GCC,arc,666,operands [ <NUM_LIT> ] = operands [ <NUM_LIT> ] ;
GCC,arc,667,}
GCC,arc,668,
GCC,arc,669,return <STR_LIT> ;
GCC,arc,670,
GCC,arc,671,}
GCC,arc,672,
GCC,arc,673,
GCC,arc,674,}
GCC,arc,675,p = &func_ptr;
GCC,arc,676,
LLVM,NVPTX,0,}
LLVM,NVPTX,1,return NewFunc;
LLVM,NVPTX,2,
LLVM,NVPTX,3,
LLVM,NVPTX,4,
LLVM,NVPTX,5,
LLVM,NVPTX,6,
LLVM,NVPTX,7,assert ( ((llvm_intrinsic not available) ||  llvm_intrinsic_return_type = llvm_intrinsic_pointer_type) && <STRING_LITERAL> <STRING_LITERAL>) ;
LLVM,NVPTX,8,
LLVM,NVPTX,9,}
LLVM,NVPTX,10,
LLVM,NVPTX,11,
LLVM,NVPTX,12,
LLVM,NVPTX,13,
LLVM,NVPTX,14,if (Current != Pool.end() && *Current == hello) {
LLVM,NVPTX,15,
LLVM,NVPTX,16,std::cout << *Str;
LLVM,NVPTX,17,
LLVM,NVPTX,18,
LLVM,NVPTX,19,
LLVM,NVPTX,20,
LLVM,NVPTX,21,;
LLVM,NVPTX,22,return createNVVMReflectPass(SmVersion + 1);
LLVM,NVPTX,23,{
LLVM,NVPTX,24,
LLVM,NVPTX,25,AU.addPreserved<StackProtector>();
LLVM,NVPTX,26,AU .addRequired < AddressSanitizer > ( ) ;
LLVM,NVPTX,27,
LLVM,NVPTX,28,AU.addRequired<MachineRegisterInfo>();
LLVM,NVPTX,29,
LLVM,NVPTX,30,
LLVM,NVPTX,31,}
LLVM,NVPTX,32,AU.addRequired<DataLayoutPass>();
LLVM,NVPTX,33,Function :: iterator I = function . begin ( ) ;
LLVM,NVPTX,34,AU.addRequired<CallGraphWrapperPass>();
LLVM,NVPTX,35,AU.addRequired<LiveVariables>() ;
LLVM,NVPTX,36,}
LLVM,NVPTX,37,if (AddMandatoryReversablePass) {
LLVM,NVPTX,38,AU.addRequired<MachineFunctionAnalysis>();
LLVM,NVPTX,39,
LLVM,NVPTX,40,
LLVM,NVPTX,41,
LLVM,NVPTX,42,return true;
LLVM,NVPTX,43,delete [] gv_array ;
LLVM,NVPTX,44,i = 0;
LLVM,NVPTX,45,OutStreamer . AddComment ( <STR_LIT> ) ;
LLVM,NVPTX,46,"printReturnValStr ( F ,O ) ;"
LLVM,NVPTX,47,
LLVM,NVPTX,48,break ;
LLVM,NVPTX,49,O << <STR_LIT> ;
LLVM,NVPTX,50,"MCTargetStreamer.emitInstruction(Inst, OS);"
LLVM,NVPTX,51,
LLVM,NVPTX,52,
LLVM,NVPTX,53,
LLVM,NVPTX,54,<< ElementSize << . <STR_LIT>
LLVM,NVPTX,55,
LLVM,NVPTX,56,if (isVec) {
LLVM,NVPTX,57,
LLVM,NVPTX,58,case Type :: FloatTyID : return <STR_LIT> ;
LLVM,NVPTX,59,
LLVM,NVPTX,60,
LLVM,NVPTX,61,
LLVM,NVPTX,62,
LLVM,NVPTX,63,O << <ISA_LIT> << RegClassStr(RC) << mapped_vr << report_fatal_error(<STR_LIT>);
LLVM,NVPTX,64,"MCOp = MCOperand :: CreateExpr ( <ISA_LIT> FloatMCExpr :: CreateConstantFPLongDouble ( Val , OutContext ) ) ;"
LLVM,NVPTX,65,{
LLVM,NVPTX,66,if (MO.isImm()) {
LLVM,NVPTX,67,temp . push_back ( GVar ) ;
LLVM,NVPTX,68,
LLVM,NVPTX,69,}
LLVM,NVPTX,70,}
LLVM,NVPTX,71,
LLVM,NVPTX,72,
LLVM,NVPTX,73,return false;
LLVM,NVPTX,74,"if ( ! I->isTerminator( ) && allocFnSeen(caller, allocMap) ) continue;"
LLVM,NVPTX,75,reader = null;
LLVM,NVPTX,76,}
LLVM,NVPTX,77,if(pos < size) {
LLVM,NVPTX,78,if ( IsNonGenericPointer ) {
LLVM,NVPTX,79,"the end of the loop, as indicated by  }"
LLVM,NVPTX,80,"printModuleLevelGV ( Globals [ <NUM_LIT> ] , OS2 ) ;"
LLVM,NVPTX,81,a closing brace '}
LLVM,NVPTX,82,}
LLVM,NVPTX,83,if ( ! LT . isLittleEndian ( ) ) {
LLVM,NVPTX,84,This case statement is missing a break;
LLVM,NVPTX,85,
LLVM,NVPTX,86,nvptxSubtarget.getDvInterface() == recordAndEmitFilenames(M);
LLVM,NVPTX,87,"Considering currentFnSym is a pointer to the current function and printReturnValStr is a function that prints the return value of a given function, the next statement could potentially be printReturnValStr(F, O);"
LLVM,NVPTX,88,
LLVM,NVPTX,89,"emitDeclaration ( F , O ) ;"
LLVM,NVPTX,90,
LLVM,NVPTX,91,
LLVM,NVPTX,92,}
LLVM,NVPTX,93,O << <VAR_REF> ;
LLVM,NVPTX,94,
LLVM,NVPTX,95,
LLVM,NVPTX,96,O << nvptxSubtarget.getRegClassName() ;
LLVM,NVPTX,97,
LLVM,NVPTX,98,
LLVM,NVPTX,99,"if ( llvm :: getReqNTIDz ( F , reqntidz ) == false ) reqntidz = <NUM_LIT> ;"
LLVM,NVPTX,100,
LLVM,NVPTX,101,
LLVM,NVPTX,102,ElementSize = TD -> <NUM_LIT> ;
LLVM,NVPTX,103,
LLVM,NVPTX,104,
LLVM,NVPTX,105,
LLVM,NVPTX,106,return reader;
LLVM,NVPTX,107,else llvm_unreachable ( <STR_LIT> ) ;
LLVM,NVPTX,108,case <STR_LIT> : break
LLVM,NVPTX,109,<STR_LIT> :
LLVM,NVPTX,110,case Instruction :: a case statement for Instruction::UDiv to handle unsigned division.
LLVM,NVPTX,111,;
LLVM,NVPTX,112,
LLVM,NVPTX,113,
LLVM,NVPTX,114,return;
LLVM,NVPTX,115,}
LLVM,NVPTX,116,}
LLVM,NVPTX,117,O << * Mang -> getSymbol ( MO . getGlobal ( ) ) ;
LLVM,NVPTX,118,"sscanf ( symbname + <NUM_LIT> , <STR_LIT> , & index ) ;"
LLVM,NVPTX,119,
LLVM,NVPTX,120,if (I->getType()->isPointerTy()) {
LLVM,NVPTX,121,O << .byte  ;
LLVM,NVPTX,122,return ;
LLVM,NVPTX,123,if ( Imm > <NUM_LIT> ) O << vecelem [ Imm % <NUM_LIT> ] ;
LLVM,NVPTX,124,
LLVM,NVPTX,125,}
LLVM,NVPTX,126,}
LLVM,NVPTX,127,
LLVM,NVPTX,128,<< the number of registers in ISA << .
LLVM,NVPTX,129,ui != ue ;
LLVM,NVPTX,130,if ( ! caller ) continue ;
LLVM,NVPTX,131,for ( auto user = ui -> getUser ( ) golden::
LLVM,NVPTX,132,either  (}
LLVM,NVPTX,133,}
LLVM,NVPTX,134,const Type * innerType = Pty -> getElementType ( ) ;
LLVM,NVPTX,135,
LLVM,NVPTX,136,}
LLVM,NVPTX,137,"<i> global_list . insert ( global_list . end ( ) , gv_array [ <NUM_LIT> ] ) ;"
LLVM,NVPTX,138,
LLVM,NVPTX,139,
LLVM,NVPTX,140,"emitFunctionBody ( F , O ) ;"
LLVM,NVPTX,141,
LLVM,NVPTX,142,
LLVM,NVPTX,143,
LLVM,NVPTX,144,to end the function definition. It would look something like: }
LLVM,NVPTX,145,O << Hello world!;
LLVM,NVPTX,146,std::string res = O.str();
LLVM,NVPTX,147,return;
LLVM,NVPTX,148,
LLVM,NVPTX,149,
LLVM,NVPTX,150,STI.setSchedModel(SchedModelFactory().createSchedModel(STI));
LLVM,NVPTX,151,
LLVM,NVPTX,152,
LLVM,NVPTX,153,O << <STR_LIT> << maxnreg << <STR_LIT> ;
LLVM,NVPTX,154,
LLVM,NVPTX,155,default : O << Unknown address space  + llvm::Twine(AddressSpace);
LLVM,NVPTX,156,end by saying: Unknown address space: <AddressSpace>.
LLVM,NVPTX,157,
LLVM,NVPTX,158,OutStreamer -> emitRawText ( OS1 . str ( ) ) ;
LLVM,NVPTX,159,}
LLVM,NVPTX,160,return Ret;
LLVM,NVPTX,161,}
LLVM,NVPTX,162,
LLVM,NVPTX,163,return <STR_LIT> ;
LLVM,NVPTX,164,return <STR_LIT ;
LLVM,NVPTX,165,
LLVM,NVPTX,166,
LLVM,NVPTX,167,if (LI.isLoopHeader(PMBB)) continue;
LLVM,NVPTX,168,RegisterAsmParser < <ISA_LIT>AsmParser > Y ( getThe<ISA_LIT>Target32 ( ) ) ;
LLVM,NVPTX,169,
LLVM,NVPTX,170,SymNamePtr = nvTM . getManagedStrPool ( ) -> getManagedString ( NextSym ) ;
LLVM,NVPTX,171,
LLVM,NVPTX,172,
LLVM,NVPTX,173,
LLVM,NVPTX,174,O << ']' ;
LLVM,NVPTX,175,}
LLVM,NVPTX,176,llvm_unreachable ( <STR_LIT> ) ;
LLVM,NVPTX,177,"if ( Modifier && strcmp( Modifier , imm) == 0 ) {"
LLVM,NVPTX,178,
LLVM,NVPTX,179,llvm_unreachable(<STR_LIT>);
LLVM,NVPTX,180,{
LLVM,NVPTX,181,
LLVM,NVPTX,182,}
LLVM,NVPTX,183,return Result;
LLVM,NVPTX,184,if (Result) {
LLVM,NVPTX,185,O << <STR_LIT> ;
LLVM,NVPTX,186,
LLVM,NVPTX,187,"VisitGlobalVariableForEmission( GV, Order, Visited, Visiting );"
LLVM,NVPTX,188,assert ( ( curpos + Num ) <= size ) ;
LLVM,NVPTX,189,"to close the for loop, possibly with a '{"
LLVM,NVPTX,190,
LLVM,NVPTX,191,return Symbols;
LLVM,NVPTX,192,}
LLVM,NVPTX,193,
LLVM,NVPTX,194,
LLVM,NVPTX,195,<NUM_LIT> }
LLVM,NVPTX,196,
LLVM,NVPTX,197,
LLVM,NVPTX,198,
LLVM,NVPTX,199,;
LLVM,NVPTX,200,"printParamName (I, paramIndex, O);"
LLVM,NVPTX,201,O << <STR_LIT> ;
LLVM,NVPTX,202,O << * (unsigned int*)(buffer + nextSymbolPos);
LLVM,NVPTX,203,}
LLVM,NVPTX,204,if (Order.empty()) {
LLVM,NVPTX,205,
LLVM,NVPTX,206,next = buffer ;
LLVM,NVPTX,207,llvm_unreachable(<STR_LIT>);
LLVM,NVPTX,208,
LLVM,NVPTX,209,"emitDefinition ( F , O ) ;"
LLVM,NVPTX,210,}
LLVM,NVPTX,211,"emitPrototypeDirective ( F , O ) ;"
LLVM,NVPTX,212,O << MF -> getFunctionNumber ( * F ) ;
LLVM,NVPTX,213,
LLVM,NVPTX,214,
LLVM,NVPTX,215,
LLVM,NVPTX,216,
LLVM,NVPTX,217,default: O << <PTR_LIT> ;
LLVM,NVPTX,218,}
LLVM,NVPTX,219,<< .align  << GVar->getAlignment();
LLVM,NVPTX,220,
LLVM,NVPTX,221,reader = new LineReader ( filename ) ;
LLVM,NVPTX,222,}
LLVM,NVPTX,223,RegisterAsmPrinter < <ISA_LIT>AsmPrinter > Z ( getThe<ISA_LIT>Target128 ( ) ) ;
LLVM,NVPTX,224,case Instruction::Sub: {
LLVM,NVPTX,225,"incomplete and `MCOp` is a variable, the next statement could be something like `MCOp->doSomething();"
LLVM,NVPTX,226,
LLVM,NVPTX,227,"MCOp = MCOperand :: createExpr ( <ISA_LIT>DoubleMCExpr :: createConstantFP ( Val , OutContext ) ) ;"
LLVM,NVPTX,228,
LLVM,NVPTX,229,O << <STR_LIT> ;
LLVM,NVPTX,230,elemtype = vtparts [ i ] . getVectorElementType ( ) ;
LLVM,NVPTX,231,EVT elemtype = vtparts [ i ] ;
LLVM,NVPTX,232,"OutStreamer -> EmitDwarfCompileUnitDirective ( i , <STR_LIT> , Dirname, Filename ) ;"
LLVM,NVPTX,233,"OutStreamer -> EmitDwarfFileDirective (i, <STR_LIT>, Filename);"
LLVM,NVPTX,234,O << <STR_LIT> ;
LLVM,NVPTX,235,O << <STR_LIT>;
LLVM,NVPTX,236,O << MI->getOperand(0).getReg() <<  is implicitly defined;
LLVM,NVPTX,237,}
LLVM,NVPTX,238,O << <STR_LIT> ;
LLVM,NVPTX,239,O << * MO . getMachineMemOperand () ;
LLVM,NVPTX,240,
LLVM,NVPTX,241,<S> Symbols . push_back ( GVar ) ;
LLVM,NVPTX,242,"is defining a class called AggBuffer, which takes in three parameters: an unsigned integer called _size, a raw_ostream reference called _O, and an ISA_LITAsmPrinter reference called _AP. The class also initializes a variable called buffer to a newly allocated unsigned character array with a size of _size and sets the size variable to _size."
LLVM,NVPTX,243,
LLVM,NVPTX,244,}
LLVM,NVPTX,245,ptr = ( unsigned char * ) CPV ;
LLVM,NVPTX,246,
LLVM,NVPTX,247,If (oneFunc == nullptr) {
LLVM,NVPTX,248,}
LLVM,NVPTX,249,stats = MMI->getQueryResult ( M );
LLVM,NVPTX,250,"emitBody(F, O);"
LLVM,NVPTX,251,
LLVM,NVPTX,252,IL.EmitVoid(Opcode.ClearVRegMapping);
LLVM,NVPTX,253,OutStreamer.Finish();
LLVM,NVPTX,254,
LLVM,NVPTX,255,O << <STR_LIT> ;
LLVM,NVPTX,256,
LLVM,NVPTX,257,case <NUM_LIT> : break ;
LLVM,NVPTX,258,assert (GVVisited.size() == M.getGlobalList().size() && Expected number of visited global variables to match total number of global variables in the module.);
LLVM,NVPTX,259,for (const GlobalVariable *GV : M.global_values()) {
LLVM,NVPTX,260,if (nvptxSubtarget.getDefaultFeatures() == <STR_LIT>) O << <STR_LIT>;
LLVM,NVPTX,261,O << Output to stream;
LLVM,NVPTX,262,}
LLVM,NVPTX,263,MCInst Inst2;
LLVM,NVPTX,264,OS << mcInst Inst;
LLVM,NVPTX,265,O << <STR_LIT> << maxntidx << <STR_LIT> ;
LLVM,NVPTX,266,
LLVM,NVPTX,267,else {
LLVM,NVPTX,268,O << <STR_LIT> ;
LLVM,NVPTX,269,O << <STR_LIT> ;
LLVM,NVPTX,270,break;
LLVM,NVPTX,271,
LLVM,NVPTX,272,return i * alignStruct ;
LLVM,NVPTX,273,
LLVM,NVPTX,274,return MCOperand :: Create (Expr);
LLVM,NVPTX,275,
LLVM,NVPTX,276,
LLVM,NVPTX,277,return false;
LLVM,NVPTX,278,
LLVM,NVPTX,279,"go to either the default case (where the lower constant function is called on the constant C), or the case Instruction::AddrSpaceCast statement (where the types are checked and an error may be reported)."
LLVM,NVPTX,280,return true ;
LLVM,NVPTX,281,"MCOp->addExpr(MCSymbolRefExpr::create(Sym, OutContext));"
LLVM,NVPTX,282,case MachineOperand :: MO_Register : MCOp = MCOperand :: CreateReg ( MO . getReg ( ) ) ;
LLVM,NVPTX,283,if ( Cexpr -> getOpcode ( ) == <STR_LIT> ) {
LLVM,NVPTX,284,"printGlobalAddress(MO.getGlobalAddress(), O);"
LLVM,NVPTX,285,
LLVM,NVPTX,286,
LLVM,NVPTX,287,O << * getSymbol ( GVar ) ;
LLVM,NVPTX,288,return ;
LLVM,NVPTX,289,"sys :: path :: append ( FullPathName , Filename ) ;"
LLVM,NVPTX,290,if ( RC -> getSize ( ) < <NUM_LIT> ) {
LLVM,NVPTX,291,for ( unsigned int j = 0 ;
LLVM,NVPTX,292,}
LLVM,NVPTX,293,if (const BasicBlock *BB = dyn_cast<BasicBlock>(U)) {
LLVM,NVPTX,294,}
LLVM,NVPTX,295,Order.push_back(GV);
LLVM,NVPTX,296,
LLVM,NVPTX,297,}
LLVM,NVPTX,298,O << <STR_LIT> ;
LLVM,NVPTX,299,O << <STR_LIT> << GVar -> getName ( ) << <STR_LIT> ;
LLVM,NVPTX,300,O << <STR_LIT> ;
LLVM,NVPTX,301,O << <STR_LIT> << sz << <STR_LIT> ;
LLVM,NVPTX,302,i++;
LLVM,NVPTX,303,
LLVM,NVPTX,304,
LLVM,NVPTX,305,return Result;
LLVM,NVPTX,306,an opening curly brace ({
LLVM,NVPTX,307,"emitSymbol(GVar, O, TD, ETy, ElementSize);"
LLVM,NVPTX,308,"alignStruct = std :: max ( alignStruct , getOpenCLAlignment ( TD , ETy ) ) ;"
LLVM,NVPTX,309,}
LLVM,NVPTX,310,valer = SDValue ( }
LLVM,NVPTX,311,if ( elemtype . isSimple ( ) ) {
LLVM,NVPTX,312,return ;
LLVM,NVPTX,313,
LLVM,NVPTX,314,a for loop: for (const User *UU : U->users())
LLVM,NVPTX,315,return true ;
LLVM,NVPTX,316,
LLVM,NVPTX,317,if ( Ty -> isAggregateType ( ) || Ty -> isVectorTy ( ) ) {
LLVM,NVPTX,318,
LLVM,NVPTX,319,O << getSymbolName ( GVar ) << <STR_LIT> ;
LLVM,NVPTX,320,
LLVM,NVPTX,321,}
LLVM,NVPTX,322,}
LLVM,NVPTX,323,
LLVM,NVPTX,324,
LLVM,NVPTX,325,
LLVM,NVPTX,326,}
LLVM,NVPTX,327,return ;
LLVM,NVPTX,328,break;
LLVM,NVPTX,329,else {
LLVM,NVPTX,330,
LLVM,NVPTX,331,
LLVM,NVPTX,332,OutStreamer.EmitRawText(M.getModuleInlineAsm());
LLVM,NVPTX,333,O << -- paramIndex ;
LLVM,NVPTX,334,if (TargetRegisterInfo::isReservedReg -1) {
LLVM,NVPTX,335,
LLVM,NVPTX,336,OutStreamer . EmitRawText ( temp . str ( ) ) ;
LLVM,NVPTX,337,temp << <INT_LIT> ;
LLVM,NVPTX,338,
LLVM,NVPTX,339,}
LLVM,NVPTX,340,
LLVM,NVPTX,341,}
LLVM,NVPTX,342,if ( GVar -> hasInitializer ( ) ) {
LLVM,NVPTX,343,}
LLVM,NVPTX,344,}
LLVM,NVPTX,345,if ( vtparts [ i ] . isVector ( ) ) {
LLVM,NVPTX,346,This snippet predicts the next statement to be O <<  ] ;
LLVM,NVPTX,347,
LLVM,NVPTX,348,while (i < 10) {
LLVM,NVPTX,349,}
LLVM,NVPTX,350,
LLVM,NVPTX,351,}
LLVM,NVPTX,352,Ret = ( <NUM_LIT> << <NUM_LIT> ) ;
LLVM,NVPTX,353,<NUM_LIT> ;
LLVM,NVPTX,354,buffer_size = _size ;
LLVM,NVPTX,355,"global_list.insert(global_list.end(), gv_array[i]);"
LLVM,NVPTX,356,
LLVM,NVPTX,357,
LLVM,NVPTX,358,
LLVM,NVPTX,359,
LLVM,NVPTX,360,std::cout << O.str();
LLVM,NVPTX,361,
LLVM,NVPTX,362,
LLVM,NVPTX,363,
LLVM,NVPTX,364,}
LLVM,NVPTX,365,
LLVM,NVPTX,366,}
LLVM,NVPTX,367,break;
LLVM,NVPTX,368,"getSymbol(GVar)->print(O, MAI);"
LLVM,NVPTX,369,
LLVM,NVPTX,370,Instruction::Add is the next statement.
LLVM,NVPTX,371,APInt API = cast < ConstantInt > ( CE -> getOperand ( <NUM_LIT> ) ) -> getValue ( ) ;
LLVM,NVPTX,372,}
LLVM,NVPTX,373,}
LLVM,NVPTX,374,
LLVM,NVPTX,375,if ( ! Result ) {
LLVM,NVPTX,376,X = U -> getOperand ( i ) ;
LLVM,NVPTX,377,"emitGlobalVariables(M, OS2, Globals, GVVisited, GVVisiting);"
LLVM,NVPTX,378,O << <STR_LIT> << sz << <STR_LIT> ;
LLVM,NVPTX,379,output  ;
LLVM,NVPTX,380,
LLVM,NVPTX,381,If ( FTy ) {
LLVM,NVPTX,382,"case Instruction :: SRem : return MCBinaryExpr :: CreateRem ( LHS , RHS , Ctx ) ;"
LLVM,NVPTX,383,
LLVM,NVPTX,384,
LLVM,NVPTX,385,}
LLVM,NVPTX,386,OutStreamer->EmitRawText(Emitting Function Virtual Registers);
LLVM,NVPTX,387,
LLVM,NVPTX,388,O << <STR_LIT> ;
LLVM,NVPTX,389,
LLVM,NVPTX,390,
LLVM,NVPTX,391,"emitDefinitions(M, Globals, GVVisited, GVVisiting);"
LLVM,NVPTX,392,}
LLVM,NVPTX,393,}
LLVM,NVPTX,394,}
LLVM,NVPTX,395,for ( i = <NUM_LIT> ;
LLVM,NVPTX,396,
LLVM,NVPTX,397,else {
LLVM,NVPTX,398,
LLVM,NVPTX,399,if (F->getName() != caller) {
LLVM,NVPTX,400,
LLVM,NVPTX,401,
LLVM,NVPTX,402,unsigned sz = elemtype.getSizeInBits();
LLVM,NVPTX,403,if ( Register :: isOpenVReg ( i ) ) {
LLVM,NVPTX,404,const std::string pairwiseNames[] = {
LLVM,NVPTX,405,
LLVM,NVPTX,406,O << <STR_LIT> ;
LLVM,NVPTX,407,}
LLVM,NVPTX,408,case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :
LLVM,NVPTX,409,}
LLVM,NVPTX,410,}
LLVM,NVPTX,411,
LLVM,NVPTX,412,O << <STR_LIT> << getOptimalAlignForParam ( Ty ) . value ( ) ;
LLVM,NVPTX,413,llvm_unreachable(<STR_LIT>);
LLVM,NVPTX,414,}
LLVM,NVPTX,415,"called with four parameters: TLI, DL, Ty, and vtparts."
LLVM,NVPTX,416,llvm_unreachable(Function already has a body);
LLVM,NVPTX,417,}
LLVM,NVPTX,418,O << <STR_LIT> << <STR_LIT> ;
LLVM,NVPTX,419,llvm_unreachable ( <STR_LIT> ) ;
LLVM,NVPTX,420,"formatValueTypes ( O , vtparts , i , j , false ) ;"
LLVM,NVPTX,421,
LLVM,NVPTX,422,"return lowerConstantForGV(Op, ProcessingGeneric);"
LLVM,NVPTX,423,
LLVM,NVPTX,424,AsmPrinter::doFinalization(M);
LLVM,NVPTX,425,ParseFile(fileName);
LLVM,NVPTX,426,
LLVM,NVPTX,427,i++;
LLVM,NVPTX,428,if ( ! Dirname . empty ( ) && ! sys :: path :: is_absolute ( Filename ) ) {
LLVM,NVPTX,429,if (isABI || isKernelFunc) {
LLVM,NVPTX,430,"Op = ConstantExpr :: getIntegerCast ( Op , TD . getIntPtrType ( CV -> getContext ( ) ) , false ) ;"
LLVM,NVPTX,431,}
LLVM,NVPTX,432,
LLVM,NVPTX,433,"ConvertDoubleToBytes ( ptr , float64 ) ;"
LLVM,NVPTX,434,
LLVM,NVPTX,435,
LLVM,NVPTX,436,
LLVM,NVPTX,437,cout << Element size is  << ElementSize << endl;
LLVM,NVPTX,438,"case Instruction :: Or : return MCBinaryExpr :: CreateOr ( LHS , RHS , Ctx ) ;"
LLVM,NVPTX,439,"sscanf ( symbname + <NUM_LIT> , <STR_LIT> , & index ) ;"
LLVM,NVPTX,440,llvm_unreachable ( <STR_LIT> ) ;
LLVM,NVPTX,441,SmallString <<NUM_LIT> > Str1;
LLVM,NVPTX,442,
LLVM,NVPTX,443,}
LLVM,NVPTX,444,llvm_unreachable ( <STR_LIT> ) ;
LLVM,NVPTX,445,
LLVM,NVPTX,446,case Instruction::Sub: {
LLVM,NVPTX,447,Instruction: GetElementPtr
LLVM,NVPTX,448,assert(Ty->isFloatingPointTy() && <STR_LIT>size = Ty->getPrimitiveSizeInBits();
LLVM,NVPTX,449,++ idx ;
LLVM,NVPTX,450,
LLVM,NVPTX,451,for (i = <NUM_LIT>;
LLVM,NVPTX,452,
LLVM,NVPTX,453,
LLVM,NVPTX,454,OutStreamer->InitToModule(M);
LLVM,NVPTX,455,O << Function definitions for  << F->getName() << :\n ;
LLVM,NVPTX,456,"emitPTXAttributeType ( ETy , O ) ;"
LLVM,NVPTX,457,O << <STR_LIT> << ElementSize ;
LLVM,NVPTX,458,
LLVM,NVPTX,459,
LLVM,NVPTX,460,"emitImplementations (M, OS2);"
LLVM,NVPTX,461,"if (PAL.paramHasAttr(paramIndex + 1, Attribute::ByVal) == true) {"
LLVM,NVPTX,462,"if (PAL.paramHasAttr(paramIndex + 1, Attribute::ByVal) == false) {"
LLVM,NVPTX,463,
LLVM,NVPTX,464,
LLVM,NVPTX,465,elemtype = vtparts [ i ] . getVectorElementType ( ) ;
LLVM,NVPTX,466,"SmallVector <EVT, 1> vtparts;"
LLVM,NVPTX,467,
LLVM,NVPTX,468,else if ( Ty -> isFloatingPointTy ( <NUM_LIT> ) ) O << <STR_LIT> ;
LLVM,NVPTX,469,
LLVM,NVPTX,470,using a switch statement to handle different types of instructions.
LLVM,NVPTX,471,}
LLVM,NVPTX,472,
LLVM,NVPTX,473,
LLVM,NVPTX,474,
LLVM,NVPTX,475,
LLVM,NVPTX,476,return Bytes;
LLVM,NVPTX,477,
LLVM,NVPTX,478,
LLVM,NVPTX,479,OutStreamer . AddComment ( StringRef ( M . getInlineAsm ( ) ) ) ;
LLVM,NVPTX,480,}
LLVM,NVPTX,481,
LLVM,NVPTX,482,O << <STR_LIT> ;
LLVM,NVPTX,483,if (i < e - <NUM_LIT>) O << <STR_LIT>;
LLVM,NVPTX,484,O << The size of the array is  << sz;
LLVM,NVPTX,485,O << <STR_LIT> << getSymbol(GVar) << ' ' << <STR_LIT> << ElementSize << ' ' << <STR_LIT>;
LLVM,NVPTX,486,
LLVM,NVPTX,487,llvm_unreachable ( ) ;
LLVM,NVPTX,488,
LLVM,NVPTX,489,return false ;
LLVM,NVPTX,490,case <STR_LIT> :
LLVM,NVPTX,491,
LLVM,NVPTX,492,totalTokens = numSymbols + numGVariables;
LLVM,NVPTX,493,}
LLVM,NVPTX,494,"bufferLEByte ( cast < Constant > ( CPV -> getValueInit ( i ) ) , <NUM_LIT> , <NUM_LIT> <NUM_LIT> ;"
LLVM,NVPTX,495,if (oneFunc = nullptr) return false;
LLVM,NVPTX,496,}
LLVM,NVPTX,497,
LLVM,NVPTX,498,vp[i] = 0;
LLVM,NVPTX,499,p [ i ] = ( unsigned char ) vp ;
LLVM,NVPTX,500,if (vp < 0) {
LLVM,NVPTX,501,Result<NUM_LIT> . insert ( U -> getOperand ( i ) ) ;
LLVM,NVPTX,502,for (i = 0;
LLVM,NVPTX,503,
LLVM,NVPTX,504,
LLVM,NVPTX,505,
LLVM,NVPTX,506,
LLVM,NVPTX,507,
LLVM,NVPTX,508,"emitFunctionBody ( F , O ) ;"
LLVM,NVPTX,509,"emitDeclaration(F, O);"
LLVM,NVPTX,510,
LLVM,NVPTX,511,
LLVM,NVPTX,512,raw_svector_ostream OS ( Str ) ;
LLVM,NVPTX,513,return 0;
LLVM,NVPTX,514,
LLVM,NVPTX,515,
LLVM,NVPTX,516,
LLVM,NVPTX,517,
LLVM,NVPTX,518,std :: string msg ;
LLVM,NVPTX,519,O << <STR_LIT> ;
LLVM,NVPTX,520,
LLVM,NVPTX,521,temp << reader -> readLine ( line ) ;
LLVM,NVPTX,522,}
LLVM,NVPTX,523,
LLVM,NVPTX,524,
LLVM,NVPTX,525,
LLVM,NVPTX,526,return name + utostr(NumBits);
LLVM,NVPTX,527,
LLVM,NVPTX,528,else {
LLVM,NVPTX,529,return Expr;
LLVM,NVPTX,530,"return MCOperand::CreateExpr(MCSymbolRefExpr::Create(Symbol, MCSymbolRefExpr::VK_None, *Ctx));"
LLVM,NVPTX,531,
LLVM,NVPTX,532,
LLVM,NVPTX,533,return true if the type of the input parameter is an image type.
LLVM,NVPTX,534,}
LLVM,NVPTX,535,break;
LLVM,NVPTX,536,fstr >> theNextLine;
LLVM,NVPTX,537,
LLVM,NVPTX,538,
LLVM,NVPTX,539,case Instruction::PtrToInt: {
LLVM,NVPTX,540,}
LLVM,NVPTX,541,std :: cout << *SymNamePtr << std::endl;
LLVM,NVPTX,542,The next statement predicts: MCOp = GetSymbolRef(OutContext.getOrCreateSymbol(StringRef(SymNamePtr->c_str()))) ;
LLVM,NVPTX,543,ends with a curly brace (}
LLVM,NVPTX,544,
LLVM,NVPTX,545,if ( !nvptxSubtarget->hasSamplerHandles() ) {
LLVM,NVPTX,546,}
LLVM,NVPTX,547,O << ']';
LLVM,NVPTX,548,return ExtraCode[<NUM_LIT>];
LLVM,NVPTX,549,
LLVM,NVPTX,550,O << lead << hexstr;
LLVM,NVPTX,551,"OS <<  +  prediction: printMCExpr(*BE.getRHS(), OS);"
LLVM,NVPTX,552,The predicted statement is }
LLVM,NVPTX,553,}
LLVM,NVPTX,554,}
LLVM,NVPTX,555,
LLVM,NVPTX,556,
LLVM,NVPTX,557,"would be lowerConstant (CPV)->print(O, MAI);"
LLVM,NVPTX,558,}
LLVM,NVPTX,559,O << 0x80 << vecelem [ Imm % <NUM_LIT> ] ;
LLVM,NVPTX,560,
LLVM,NVPTX,561,}
LLVM,NVPTX,562,filenameMap [ Filename ] = i ;
LLVM,NVPTX,563,nvptxSubtarget.initializeSubtarget();
LLVM,NVPTX,564,return nvptxSubtarget->initC;
LLVM,NVPTX,565,std::string rcname = get<ISA_LIT>RegClassName(RC);
LLVM,NVPTX,566,
LLVM,NVPTX,567,"incomplete and does not follow any specific structure, it is not possible to accurately predict the next statement. Some possible next statements could be another closing curly bracket (}"
LLVM,NVPTX,568,
LLVM,NVPTX,569,}
LLVM,NVPTX,570,if (!caller->isDeclaration()) {
LLVM,NVPTX,571,
LLVM,NVPTX,572,
LLVM,NVPTX,573,
LLVM,NVPTX,574,}
LLVM,NVPTX,575,
LLVM,NVPTX,576,the closing brace }
LLVM,NVPTX,577,ValidNameStream << C ;
LLVM,NVPTX,578,}
LLVM,NVPTX,579,
LLVM,NVPTX,580,}
LLVM,NVPTX,581,
LLVM,NVPTX,582,}
LLVM,NVPTX,583,return GV;
LLVM,NVPTX,584,implemented here }
LLVM,NVPTX,585,AU . setCheckingStateAtIO () ;
LLVM,NVPTX,586,return InstructionCountPass;
LLVM,NVPTX,587,
LLVM,NVPTX,588,
LLVM,NVPTX,589,
LLVM,NVPTX,590,
LLVM,NVPTX,591,
LLVM,NVPTX,592,
LLVM,NVPTX,593,Cast->eraseFromParent();
LLVM,NVPTX,594,if ( GlobalAlias * GA = dyn_cast < GlobalAlias > ( MI -> getOperand ( Idx ) ) ) {
LLVM,NVPTX,595,}
LLVM,NVPTX,596,"Cast -> setOperand ( <NUM_LIT , NewGEPCE ) ;"
LLVM,NVPTX,597,}
LLVM,NVPTX,598,
LLVM,NVPTX,599,if ( Instruction * I = dyn_cast < Instruction > ( V ) ) {
LLVM,NVPTX,600,"if (AddrSpaceCastOperator *ASC = dyn_cast<AddrSpaceCastOperator>(V)) return hoistAddrSpaceCastFromAddrSpaceCast(ASC, Depth);"
LLVM,NVPTX,601,}
LLVM,NVPTX,602,"Value * NewBC = new AddrSpaceCastInst ( Src , TypeOfNewCast , <STR_LIT> , nullptr ) ;"
LLVM,NVPTX,603,return true;
LLVM,NVPTX,604,GEP->replaceAllUsesWith(NewASC);
LLVM,NVPTX,605,return true;
LLVM,NVPTX,606,}
LLVM,NVPTX,607,return Changed;
LLVM,NVPTX,608,"return hoistAddrSpaceCastFromInst(I, Depth);"
LLVM,NVPTX,609,
LLVM,NVPTX,610,
LLVM,NVPTX,611,
LLVM,NVPTX,612,DestTy->getElementType();
LLVM,NVPTX,613,return doFavorNonGenericAddrSpaces;
LLVM,NVPTX,614,}
LLVM,NVPTX,615,}
LLVM,NVPTX,616,}
LLVM,NVPTX,617,}
LLVM,NVPTX,618,
LLVM,NVPTX,619,... }
LLVM,NVPTX,620,
LLVM,NVPTX,621,
LLVM,NVPTX,622,< s > const MachineFrameInfo & MFI = MF.getFrameInfo();
LLVM,NVPTX,623,return;
LLVM,NVPTX,624,return true;
LLVM,NVPTX,625,if (MF.getFrameInfo().hasVarSizedObjects()) {
LLVM,NVPTX,626,}
LLVM,NVPTX,627,
LLVM,NVPTX,628,if ( MFI . isFixedObjectIndex ( FI ) {
LLVM,NVPTX,629,return }
LLVM,NVPTX,630,
LLVM,NVPTX,631,
LLVM,NVPTX,632,return is64bit;
LLVM,NVPTX,633,
LLVM,NVPTX,634,return MFI.getObjectOffset(fI);
LLVM,NVPTX,635,
LLVM,NVPTX,636,<STR_LIT>).addReg(<STR_LIT>).addImm(0);
LLVM,NVPTX,637,"MI->addReg(<STR_LIT>, RegState::Kill);"
LLVM,NVPTX,638,
LLVM,NVPTX,639,
LLVM,NVPTX,640,"BuildMI (MBB, MI, dl, tm .getInstrInfo()->get(<STR_LIT>), <STR_LIT>).addReg(<STR_LIT>).addImm(<VAL>);"
LLVM,NVPTX,641,
LLVM,NVPTX,642,
LLVM,NVPTX,643,}
LLVM,NVPTX,644,
LLVM,NVPTX,645,
LLVM,NVPTX,647,
LLVM,NVPTX,648,
LLVM,NVPTX,649,"TII -> getFrameInstrReference(MFI, FrameReg);"
LLVM,NVPTX,650,
LLVM,NVPTX,651,
LLVM,NVPTX,652,return STI.is64Bit() ? 1 : 0;
LLVM,NVPTX,653,
LLVM,NVPTX,654,
LLVM,NVPTX,655,
LLVM,NVPTX,656,Function *Func = M.getFunction(my_function);
LLVM,NVPTX,657,else {
LLVM,NVPTX,658,NewOperand = OperandChanged ? NewOperand : Operand;
LLVM,NVPTX,659,}
LLVM,NVPTX,660,
LLVM,NVPTX,661,for the function definition: }
LLVM,NVPTX,662,
LLVM,NVPTX,663,}
LLVM,NVPTX,664,
LLVM,NVPTX,665,"CVTA = Builder . CreateBitCast ( CVTA , DestTy , <STR_LIT> ) ;"
LLVM,NVPTX,666,
LLVM,NVPTX,667,
LLVM,NVPTX,668,a closing bracket (}
LLVM,NVPTX,669,}
LLVM,NVPTX,670,
LLVM,NVPTX,671,GV -> eraseFromParent ( ) ;
LLVM,NVPTX,672,
LLVM,NVPTX,673,}
LLVM,NVPTX,674,return NewValue;
LLVM,NVPTX,675,return C;
LLVM,NVPTX,676,
LLVM,NVPTX,677,ValueToValueMapTy VM ;
LLVM,NVPTX,678,"return Builder . CreateGEP ( C -> getPointerOperand ( ) , NewOperands ) ;"
LLVM,NVPTX,679,
LLVM,NVPTX,680,{
LLVM,NVPTX,681,
LLVM,NVPTX,682,
LLVM,NVPTX,683,if (GVMap.empty()) {
LLVM,NVPTX,684,<i>[Expected output:]</i> This code continues to check each BasicBlock and replace any constants with the values from the ConstantToValueMap.
LLVM,NVPTX,685,
LLVM,NVPTX,686,"Function *CVTAFunction = Function::Create(FunctionType::get(DestTy, ParamTypes, false), Function::ExternalLinkage, <STR_LIT>, M);"
LLVM,NVPTX,687,i < e;
LLVM,NVPTX,688,I != E ;
LLVM,NVPTX,689,
LLVM,NVPTX,690,return new GenericToNVVMPass();
LLVM,NVPTX,691,}
LLVM,NVPTX,692,exit();
LLVM,NVPTX,693,Superclass::getAnalysisUsage(AU);
LLVM,NVPTX,694,
LLVM,NVPTX,695,if (GV != nullptr) {
LLVM,NVPTX,696,
LLVM,NVPTX,697,
LLVM,NVPTX,698,Value * NewValue = PoisonValue :: get ( C -> getType ( ) ) ;
LLVM,NVPTX,699,if ( Name . startswith ( <STR_LIT> ) ) {
LLVM,NVPTX,700,
LLVM,NVPTX,701,}
LLVM,NVPTX,702,}
LLVM,NVPTX,703,}
LLVM,NVPTX,704,
LLVM,NVPTX,705,
LLVM,NVPTX,706,}
LLVM,NVPTX,707,
LLVM,NVPTX,708,
LLVM,NVPTX,709,<i> return true ;
LLVM,NVPTX,710,
LLVM,NVPTX,711,"BranchInst::Create (Dest, BI);"
LLVM,NVPTX,712,
LLVM,NVPTX,713,return Changed ;
LLVM,NVPTX,714,return false;
LLVM,NVPTX,715,
LLVM,NVPTX,716,
LLVM,NVPTX,717,if (isa<Argument>(V)) {
LLVM,NVPTX,718,
LLVM,NVPTX,719,}
LLVM,NVPTX,720,}
LLVM,NVPTX,721,PostorderStack}
LLVM,NVPTX,722,"appendsGenericAddressExpressionToPostorderStack ( I . getOperand ( <NUM_LIT> ) , & PostorderStack , & Visited ) ;"
LLVM,NVPTX,723,returned.
LLVM,NVPTX,724,{
LLVM,NVPTX,725,
LLVM,NVPTX,726,
LLVM,NVPTX,727,switch ( cast <Operator>(V).getOpcode() ) {
LLVM,NVPTX,728,return AS1;
LLVM,NVPTX,729,s <ISA_LIT> FinalizeAddressSpaces ( ) : FunctionPass ( ID ) {
LLVM,NVPTX,730,
LLVM,NVPTX,731,return UndefValue::get(Operand->getType()->getPointerElementType()->getPointerTo(NewAddrSpace));
LLVM,NVPTX,732,"I -> replaceUsesOfWith ( V , NewV ) ;"
LLVM,NVPTX,733,for (BasicBlock &BB : F) {
LLVM,NVPTX,734,
LLVM,NVPTX,735,if (NewAS < OldAS) {
LLVM,NVPTX,736,
LLVM,NVPTX,737,
LLVM,NVPTX,738,
LLVM,NVPTX,739,}
LLVM,NVPTX,740,}
LLVM,NVPTX,741,O << markup ( <EXPR> ) << formatExpr ( Op . getExpr ( ) ) << markup ( <EXPR> ) ;
LLVM,NVPTX,742,
LLVM,NVPTX,743,OS << <STR_LIT> ;
LLVM,NVPTX,744,"printError ( MI , OS ) ;"
LLVM,NVPTX,745,case <STR_LIT> :: RZ : O << <STR_LIT> ;
LLVM,NVPTX,746,
LLVM,NVPTX,747,
LLVM,NVPTX,748,OS << RegNo;
LLVM,NVPTX,749,
LLVM,NVPTX,750,break;
LLVM,NVPTX,751,O << <STR_LIT> ;
LLVM,NVPTX,752,break;
LLVM,NVPTX,753,}
LLVM,NVPTX,754,
LLVM,NVPTX,755,O << default ;
LLVM,NVPTX,756,"printOperand(MI, OpNum + <NUM_LIT> + 1, O);"
LLVM,NVPTX,757,assert ( Op . isExpr ( ) && <STR_LIT> ) ;
LLVM,NVPTX,758,
LLVM,NVPTX,759,}
LLVM,NVPTX,760,
LLVM,NVPTX,761,}
LLVM,NVPTX,762,return <ISA_LIT>RegInfo ( * TM . getSubtargetImpl ( ) ) ;
LLVM,NVPTX,763,
LLVM,NVPTX,764,
LLVM,NVPTX,765,
LLVM,NVPTX,766,Op = ( SrcRC == & <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ;
LLVM,NVPTX,767,}
LLVM,NVPTX,768,"BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . add ( Cond [ <NUM_LIT> ] ) . addMBB ( FBB ) ;"
LLVM,NVPTX,769,
LLVM,NVPTX,770,}
LLVM,NVPTX,771,
LLVM,NVPTX,772,
LLVM,NVPTX,773,a return or an end curly brace (}
LLVM,NVPTX,774,}
LLVM,NVPTX,775,
LLVM,NVPTX,776,}
LLVM,NVPTX,777,
LLVM,NVPTX,778,return <NUM_LIT>;
LLVM,NVPTX,779,
LLVM,NVPTX,780,"BuildMI(&MBB, DL, get(<STR_LIT>)).addMBB(FBB);"
LLVM,NVPTX,781,
LLVM,NVPTX,782,
LLVM,NVPTX,783,}
LLVM,NVPTX,784,I = LastInst ;
LLVM,NVPTX,785,return true;
LLVM,NVPTX,786,}
LLVM,NVPTX,787,
LLVM,NVPTX,788,"Probably something along the lines of: Otherwise, execute the following instructions."
LLVM,NVPTX,789,"BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;"
LLVM,NVPTX,790,
LLVM,NVPTX,791,}
LLVM,NVPTX,792,
LLVM,NVPTX,793,}
LLVM,NVPTX,794,TBB = LastInst.getOperand(<NUM_LIT>).getMBB();
LLVM,NVPTX,795,return true;
LLVM,NVPTX,796,
LLVM,NVPTX,797,NextStatement: if ( SecondLastInst -
LLVM,NVPTX,798,
LLVM,NVPTX,799,
LLVM,NVPTX,800,return MI.getOperand(<NUM_LIT>).getImm();
LLVM,NVPTX,801,
LLVM,NVPTX,802,const const <ISA_LIT>RegisterInfo & getRegisterInfo ( ) const {
LLVM,NVPTX,803,"BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addMBB ( FBB ) ;"
LLVM,NVPTX,804,}
LLVM,NVPTX,805,
LLVM,NVPTX,806,
LLVM,NVPTX,807,}
LLVM,NVPTX,808,MachineOperand src = MI.getOperand(<NUM_LIT>);
LLVM,NVPTX,809,if(!isStore) return 0;
LLVM,NVPTX,810,
LLVM,NVPTX,811,
LLVM,NVPTX,812,
LLVM,NVPTX,813,
LLVM,NVPTX,814,
LLVM,NVPTX,815,
LLVM,NVPTX,816,return ProcessPass;
LLVM,NVPTX,817,"likely return the result of the SelectionDAGISel::runOnMachineFunction function, possibly using the Subtarget variable obtained through the static_cast."
LLVM,NVPTX,818,SDValue Result = Node;
LLVM,NVPTX,819,
LLVM,NVPTX,820,"the call to the allowUnsafeFPMath() function, which returns true or false."
LLVM,NVPTX,821,
LLVM,NVPTX,822,if ( ! IsKernelFn && N -> getValueType ( ) == VoidTy ) {
LLVM,NVPTX,823,
LLVM,NVPTX,824,return false;
LLVM,NVPTX,825,
LLVM,NVPTX,826,}
LLVM,NVPTX,827,return IsSigned ? <STR_LIT> : <STR_LIT> ;
LLVM,NVPTX,828,default : llvm_unreachable ( <STR_LIT> ) ;
LLVM,NVPTX,829,return Subtarget->hasDivF32() ? 0 : -1
LLVM,NVPTX,830,"return CurDAG -> getTargetConstant ( Imm , DL , <INT32> ) ;"
LLVM,NVPTX,831,;
LLVM,NVPTX,832,
LLVM,NVPTX,833,}
LLVM,NVPTX,834,case <STR_LIT> : return CmpMode :: LE ;
LLVM,NVPTX,835,
LLVM,NVPTX,836,return the result of the SelectionDAGISel::runOnMachineFunction(MF) function.
LLVM,NVPTX,837,Subtarget->addPassesToEmitMC();
LLVM,NVPTX,838,return false;
LLVM,NVPTX,839,return false;
LLVM,NVPTX,840,}
LLVM,NVPTX,841,}
LLVM,NVPTX,842,if (OpNode->getOpcode() == ISD::ADD) {
LLVM,NVPTX,843,
LLVM,NVPTX,844,
LLVM,NVPTX,845,Opc = TM.is64Bit() ? <STR_LIT> : <STR_LIT>;
LLVM,NVPTX,846,
LLVM,NVPTX,847,
LLVM,NVPTX,848,return false;
LLVM,NVPTX,849,
LLVM,NVPTX,850,return nullptr;
LLVM,NVPTX,851,
LLVM,NVPTX,852,else return true;
LLVM,NVPTX,853,
LLVM,NVPTX,854,}
LLVM,NVPTX,855,break;
LLVM,NVPTX,856,"CurDAG -> setNodeMemRefs ( cast < MachineSDNode > ( <ISA_LIT>LD ) , {"
LLVM,NVPTX,857,"Opcode = pickOpcodeForVT(MemVT.getSimpleVT().SimpleTy, <STR_LIT>, <STR_LIT>, <STR_LIT>, <STR_LIT>, <STR_LIT>, <STR_LIT>, <STR_LIT>, None);"
LLVM,NVPTX,858,SDValue Ops [ ] = {
LLVM,NVPTX,859,
LLVM,NVPTX,860,
LLVM,NVPTX,861,
LLVM,NVPTX,862,
LLVM,NVPTX,863,return false;
LLVM,NVPTX,864,
LLVM,NVPTX,865,
LLVM,NVPTX,866,
LLVM,NVPTX,867,
LLVM,NVPTX,868,default;
LLVM,NVPTX,869,
LLVM,NVPTX,870,if (Addr.getOpcode() == <STR_LIT> && Addr.getOpcode() == <ADD_LIT>) {
LLVM,NVPTX,871,return true;
LLVM,NVPTX,872,
LLVM,NVPTX,873,break ;
LLVM,NVPTX,874,break ;
LLVM,NVPTX,875,break ;
LLVM,NVPTX,876,}
LLVM,NVPTX,877,
LLVM,NVPTX,878,
LLVM,NVPTX,879,"Opcode = pickOpcodeForVT ( EltVT . getSimpleVT ( ) . SimpleTy , <STR_LIT> , <STR_LIT> , None , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , None ) ;"
LLVM,NVPTX,880,"Ops [ <NUM_LIT> ] = SDValue ( Cvt , <NUM_LIT> ) ;"
LLVM,NVPTX,881,"Ops [ <NUM_LIT> ] = SDValue ( Cvt , <NUM_LIT> ) ;"
LLVM,NVPTX,882,default : return false ;
LLVM,NVPTX,883,"case <STR_LIT> : Opcode = pickOpcodeForVT ( EltVT . getSimpleVT ( ) . SimpleTy , <STR_LIT> , <STR_LIT> , <STR_LIT> , None , <STR_LIT> , <STR_LIT> , <STR_LIT> , None ) ;"
LLVM,NVPTX,884,
LLVM,NVPTX,885,}
LLVM,NVPTX,886,doFMAF128AGG = ( OptLevel > <NUM_LIT> ) && Subtarget . hasFMAF128 ( ) && ( FMAContractLevel == <NUM_LIT> ) ;
LLVM,NVPTX,887,
LLVM,NVPTX,888,ResNode = SelectStoreParam ( N ) ;
LLVM,NVPTX,889,Opc = <STR_LIT> ;
LLVM,NVPTX,890,
LLVM,NVPTX,891,
LLVM,NVPTX,892,}
LLVM,NVPTX,893,if ( spN == 0 ) {
LLVM,NVPTX,894,
LLVM,NVPTX,895,return NULL;
LLVM,NVPTX,896,}
LLVM,NVPTX,897,
LLVM,NVPTX,898,return nullptr;
LLVM,NVPTX,899,case <STR_LIT> : Opc = <STR_LIT> ;
LLVM,NVPTX,900,break ;
LLVM,NVPTX,901,Opcode = <STR_LIT> ;
LLVM,NVPTX,902,"return CurDAG -> getMachineNode ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> , GlobalVal ) ;"
LLVM,NVPTX,903,
LLVM,NVPTX,904,if ( F && F -> <BOP_LIT> ) {
LLVM,NVPTX,905,
LLVM,NVPTX,906,return true ;
LLVM,NVPTX,907,return TargetMachine::getSubtargetImpl()->hasFMA();
LLVM,NVPTX,908,
LLVM,NVPTX,909,
LLVM,NVPTX,910,Case llvm :: ADDRESS_SPACE_CONST : return <STR_LIT> :: CONSTANT ;
LLVM,NVPTX,911,if (Subtarget.hasAddressSpace1024()) {
LLVM,NVPTX,912,
LLVM,NVPTX,913,"CurDAG->getMachineNode(Opc, SDLoc(N), N->getValueType(<NUM_LIT>), Src);"
LLVM,NVPTX,914,else {
LLVM,NVPTX,915,break ;
LLVM,NVPTX,916,case <STR_LIT> : Opcode = <STR_LIT> ;
LLVM,NVPTX,917,
LLVM,NVPTX,918,case <STR_LIT> : Opcode = <STR_LIT> ;
LLVM,NVPTX,919,return isa<ConstantAddrSpaceCastInst>(Src);
LLVM,NVPTX,920,<STR_LIT> :: LOCAL
LLVM,NVPTX,921,
LLVM,NVPTX,922,
LLVM,NVPTX,923,if ( Addr.getValueType() == MVT::i32 )
LLVM,NVPTX,924,return true;
LLVM,NVPTX,925,return false ;
LLVM,NVPTX,926,return false;
LLVM,NVPTX,927,
LLVM,NVPTX,928,}
LLVM,NVPTX,929,<STR_LIT> Retval = <STR_LIT> }
LLVM,NVPTX,930,break ;
LLVM,NVPTX,931,default : return false ;
LLVM,NVPTX,932,
LLVM,NVPTX,933,:: PARAMETER ;
LLVM,NVPTX,934,ResNode = SelectStoreVector ( N ) ;
LLVM,NVPTX,935,case <STR_LIT> : Opcode = <STR_LIT> ;
LLVM,NVPTX,936,SDValue Ops [ ] = {
LLVM,NVPTX,937,break ;
LLVM,NVPTX,938,break ;
LLVM,NVPTX,939,return;
LLVM,NVPTX,940,Opc = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ;
LLVM,NVPTX,941,"return CurDAG -> getMachineNode (Opc, SDLoc (N), N ->getValueType(N), Src);"
LLVM,NVPTX,942,}
LLVM,NVPTX,943,}
LLVM,NVPTX,944,case <STR_LIT> :  ResNode = SelectTextureIntrinsic ( N ) ;
LLVM,NVPTX,945,
LLVM,NVPTX,946,case ADDRESS_SPACE_SHARED : Opc = TM . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ;
LLVM,NVPTX,947,if ( VecSize > <NUM_LIT>) {
LLVM,NVPTX,948,case <NUM_LIT> : switch ( MemVT . getSimpleVT ( ) . SimpleTy ) {
LLVM,NVPTX,949,if ( Variant == WMMA_VARIANT_BVAR ) Variant = WMMA_VARIANT_BVAR_STRIDE ;
LLVM,NVPTX,950,"OpcodeIndex, OpcodeIndex }"
LLVM,NVPTX,951,if (ConstantSDNode *MaskConst = dyn_cast<ConstantSDNode>(MaskOp)) {
LLVM,NVPTX,952,
LLVM,NVPTX,953,[s] case <NUM_LIT+1>:
LLVM,NVPTX,954,
LLVM,NVPTX,955,}
LLVM,NVPTX,956,
LLVM,NVPTX,957,return true;
LLVM,NVPTX,958,.push_back(C);
LLVM,NVPTX,959,
LLVM,NVPTX,960,}
LLVM,NVPTX,961,case <STR_LIT> : Opcode = <STR_LIT> ;
LLVM,NVPTX,962,
LLVM,NVPTX,963,break ;
LLVM,NVPTX,964,return false ;
LLVM,NVPTX,965,if (IsKernelFn) {
LLVM,NVPTX,966,
LLVM,NVPTX,967,}
LLVM,NVPTX,968,
LLVM,NVPTX,969,if ( OptLevel == <FLOAT_LIT> ) return false ;
LLVM,NVPTX,970,return allowUnsafeFPMath(MF);
LLVM,NVPTX,971,
LLVM,NVPTX,972,return 0;
LLVM,NVPTX,973,VTs . push_back ( EltVT ) ;
LLVM,NVPTX,974,
LLVM,NVPTX,975,
LLVM,NVPTX,976,
LLVM,NVPTX,977,}
LLVM,NVPTX,978,}
LLVM,NVPTX,979,
LLVM,NVPTX,980,
LLVM,NVPTX,981,"if (ExtraSteps == ReciprocalEstimate::Enabled && Ftz) return ReciprocalEstimateOp(SDLoc(Operand), VT, DAG.getNode(ISD::FDiv, DL, VT, DAG.getConstant(1, DL), Operand), ExtraSteps);"
LLVM,NVPTX,982,
LLVM,NVPTX,983,if (!context) {
LLVM,NVPTX,984,if (STy->isSized()) {
LLVM,NVPTX,985,
LLVM,NVPTX,986,
LLVM,NVPTX,987,else return nullptr;
LLVM,NVPTX,988,
LLVM,NVPTX,989,"j+<STR_LIT>, dl)));"
LLVM,NVPTX,990,"return DAG.getSelectCC(dl, Index, DAG.getIntPtrConstant(<NUM_LIT>, dl), E0, E1, <STR_LIT>::SETNE);"
LLVM,NVPTX,991,VecIdx = -1;
LLVM,NVPTX,992,"DAG.getStore(Op.getOperand(0), SDLoc(Op), SDValue(Op.getOperand(1), 0));"
LLVM,NVPTX,993,assert(LD->isUnindexed());
LLVM,NVPTX,994,Default: llvm_unreachable ( <STR_LIT> ) ;
LLVM,NVPTX,995,}
LLVM,NVPTX,996,
LLVM,NVPTX,997,assert (Tmp2.getValueType() == <STR_LIT2>);
LLVM,NVPTX,998,
LLVM,NVPTX,999,Ops . push_back ( E0 ) ;
LLVM,NVPTX,1000,N1 -> getFormalName ( ) ;
LLVM,NVPTX,1001,else return SDValue();
LLVM,NVPTX,1002,if ( AddTo ) {
LLVM,NVPTX,1003,
LLVM,NVPTX,1004,default: break;
LLVM,NVPTX,1005,Return Ret;
LLVM,NVPTX,1006,}
LLVM,NVPTX,1007,
LLVM,NVPTX,1008,"return SDValue ( N , B ) ;"
LLVM,NVPTX,1009,
LLVM,NVPTX,1010,SDValue LoadChain = NewLD.getValue(NumElts);
LLVM,NVPTX,1011,LD = NewLD ;
LLVM,NVPTX,1012,}
LLVM,NVPTX,1013,
LLVM,NVPTX,1014,}
LLVM,NVPTX,1015,
LLVM,NVPTX,1016,}
LLVM,NVPTX,1017,}
LLVM,NVPTX,1018,
LLVM,NVPTX,1019,
LLVM,NVPTX,1020,"return <EltVT, Off> ;"
LLVM,NVPTX,1021,
LLVM,NVPTX,1022,}
LLVM,NVPTX,1023,
LLVM,NVPTX,1024,"Based on the code snippet, the next statement might be <return>);"
LLVM,NVPTX,1025,return the result of the TargetLoweringBase::getPreferredVectorAction function with the input parameter VT.
LLVM,NVPTX,1026,
LLVM,NVPTX,1027,continue;
LLVM,NVPTX,1028,"return LowerFROUND64 ( Op , DAG ) ;"
LLVM,NVPTX,1029,"SDValue RoundedA = DAG.getNode(<STR_LIT>, SL, VT, IsLarge, A, RoundedA);"
LLVM,NVPTX,1030,<NUM_LIT> = <NUM_LIT> + <NUM_LIT> ;
LLVM,NVPTX,1031,
LLVM,NVPTX,1032,"auto PtrVT = getPointerTy(DAG.getDataLayout(), GAN->getAddressSpace());"
LLVM,NVPTX,1033,"return DAG.getNode( ISD::Constant, dl, PtrVT, Op );"
LLVM,NVPTX,1034,SDValue Chain = Load -> getChain ( ) ;
LLVM,NVPTX,1035,
LLVM,NVPTX,1036,
LLVM,NVPTX,1037,Op = <STR_LIT> ;
LLVM,NVPTX,1038,"Chain = DAG.getNode(Op, dl, MVT::Other, StoreOperands);"
LLVM,NVPTX,1039,"if (VT == <STR_LIT>) return LowerSTOREi8(Op, DAG);"
LLVM,NVPTX,1040,return false;
LLVM,NVPTX,1041,}
LLVM,NVPTX,1042,
LLVM,NVPTX,1043,(}
LLVM,NVPTX,1044,return F && TO.AllowFMA;
LLVM,NVPTX,1045,return false ;
LLVM,NVPTX,1046,
LLVM,NVPTX,1047,
LLVM,NVPTX,1048,return !(CI->getSExtValue() > std::numeric_limits<int>::max());
LLVM,NVPTX,1049,if ( Offsets ) Offsets -> push_back ( Off ) ;
LLVM,NVPTX,1050,}
LLVM,NVPTX,1051,return C_Register ;
LLVM,NVPTX,1052,return ParamStr;
LLVM,NVPTX,1053,std::string ParamName = SavedStr->c_str();
LLVM,NVPTX,1054,return TargetLoweringBase::getPreferredVectorAction(VT);
LLVM,NVPTX,1055,if ( VT . getVectorNumElements ( ) != <NUM_LIT> && VT . getScalarType ( ) == <STR_LIT> ) {
LLVM,NVPTX,1056,<NUM_LIT>. O << <STR_LIT> << <STR_LIT> << sz << <STR_LIT> ;
LLVM,NVPTX,1057,
LLVM,NVPTX,1058,
LLVM,NVPTX,1059,
LLVM,NVPTX,1060,}
LLVM,NVPTX,1061,return false;
LLVM,NVPTX,1062,return true ;
LLVM,NVPTX,1063,return;
LLVM,NVPTX,1064,else return;
LLVM,NVPTX,1065,{
LLVM,NVPTX,1066,SDValue Val = Node->getOperand(i);
LLVM,NVPTX,1067,
LLVM,NVPTX,1068,"else if ( Op . getValueType ( ) == MVT :: i8 ) return LowerLOADi8 ( Op , DAG ) ;"
LLVM,NVPTX,1069,
LLVM,NVPTX,1070,"probably be to call a function on the SDValue Ops array. For example, it could be something like: SDValue finalResult = DAG.combineNodes(Ops);"
LLVM,NVPTX,1071,"Op1 = DAG .getNode( <STR_LIT> , DL , <STR_LIT> , Op1) ;"
LLVM,NVPTX,1072,
LLVM,NVPTX,1073,"return DAG.getNode(<STR_LIT>, dl, VT, TrueVal, FalseVal);"
LLVM,NVPTX,1074,}
LLVM,NVPTX,1075,"SDValue Result = DAG.getNode(<STR_LIT>, dl, VT, Ops, <NUM_LIT>);"
LLVM,NVPTX,1076,
LLVM,NVPTX,1077,
LLVM,NVPTX,1078,"Tmp3 = DAG .getNode(<ADDR_SPACE>, dl, <ADDR_SPACE>, Tmp3);"
LLVM,NVPTX,1079,return SDValue(Ops) ;
LLVM,NVPTX,1080,"return SDValue(MemSD, <NUM_LIT>);"
LLVM,NVPTX,1081,
LLVM,NVPTX,1082,return Result;
LLVM,NVPTX,1083,break ;
LLVM,NVPTX,1084,
LLVM,NVPTX,1085,
LLVM,NVPTX,1086,"case <STR_LIT> : return PerformSELECTCombine ( N , DCI ) ;"
LLVM,NVPTX,1087,
LLVM,NVPTX,1088,}
LLVM,NVPTX,1089,}
LLVM,NVPTX,1090,
LLVM,NVPTX,1091,
LLVM,NVPTX,1092,
LLVM,NVPTX,1093,SDValue Res = NewLD.getValue(i+1);
LLVM,NVPTX,1094,break;
LLVM,NVPTX,1095,
LLVM,NVPTX,1096,
LLVM,NVPTX,1097,DemotedVT = MulType ;
LLVM,NVPTX,1098,delete static_cast < < ISA_LIT > Section * > ( DwarfRangesSection ) ;
LLVM,NVPTX,1099,return true;
LLVM,NVPTX,1100,
LLVM,NVPTX,1101,
LLVM,NVPTX,1102,else return UnknownStatement;
LLVM,NVPTX,1103,
LLVM,NVPTX,1104,
LLVM,NVPTX,1105,[STR_LIT] O << hold;
LLVM,NVPTX,1106,O << PTy->getElementType()->getCanonicalType()->getAsString() <<  * ;
LLVM,NVPTX,1107,
LLVM,NVPTX,1108,if ( ! first ) {
LLVM,NVPTX,1109,O <<  {
LLVM,NVPTX,1110,Possible prediction:
LLVM,NVPTX,1111,else {
LLVM,NVPTX,1112,return MF . setDenormalMode ( APFloat :: IEEEdouble ( ) ) == DenormalMode :: FlushToZero ;
LLVM,NVPTX,1113,
LLVM,NVPTX,1114,elems = cast < VectorType > ( ETy ) -> getNumElements ( ) ;
LLVM,NVPTX,1115,
LLVM,NVPTX,1116,
LLVM,NVPTX,1117,
LLVM,NVPTX,1118,return true ;
LLVM,NVPTX,1119,
LLVM,NVPTX,1120,
LLVM,NVPTX,1121,
LLVM,NVPTX,1122,return;
LLVM,NVPTX,1123,
LLVM,NVPTX,1124,}
LLVM,NVPTX,1125,}
LLVM,NVPTX,1126,"return DAG.getNode(LOAD, dl, getPointerTy(), Op);"
LLVM,NVPTX,1127,"case <STR_LIT> : return DAG . getNode ( <INITIAL> , SDLoc ( Op ): Error: Expected expression after 'Op' }"
LLVM,NVPTX,1128,"case <STR_LIT> : return LowerCONCAT_VECTORS ( Op , DAG ) ;"
LLVM,NVPTX,1129,
LLVM,NVPTX,1130,"DAG.getMergeValues(Ops, SDLoc(Op));"
LLVM,NVPTX,1131,"return DAG.getMergeValues(Ops, SDLoc(Op));"
LLVM,NVPTX,1132,"if (VT == <INT_LIT> ) return LowerSTOREi32( Op , DAG ) ;"
LLVM,NVPTX,1133,F.getAttribute(StringLiteral).getValueAsBool();
LLVM,NVPTX,1134,if (F.getDebugLoc()) return false;
LLVM,NVPTX,1135,
LLVM,NVPTX,1136,
LLVM,NVPTX,1137,O << <STR_LIT> << align << <NUM_LIT> ;
LLVM,NVPTX,1138,}
LLVM,NVPTX,1139,
LLVM,NVPTX,1140,std::cout << The type is not a pointer or there is no context. << std::endl;
LLVM,NVPTX,1141,if (PTy != nullptr) {
LLVM,NVPTX,1142,return false;
LLVM,NVPTX,1143,case <NUM_LIT> : Op = <STR_LIT> ;
LLVM,NVPTX,1144,StoreOperands.clear();
LLVM,NVPTX,1145,SDValue tempVal = SDValue();
LLVM,NVPTX,1146,SDValue ( ) ;
LLVM,NVPTX,1147,"SmallVector < SDValue , <NUM_LIT> > OtherOps ( N -> op_begin ( ) , N -> op_end ( ) ) ;"
LLVM,NVPTX,1148,}
LLVM,NVPTX,1149,return TempVTs[i];
LLVM,NVPTX,1150,
LLVM,NVPTX,1151,if ( isa < Function > ( CalleeV ) ) DirectCallee = CalleeV ;
LLVM,NVPTX,1152,return C_RegisterClass;
LLVM,NVPTX,1153,
LLVM,NVPTX,1154,
LLVM,NVPTX,1155,"< s > return EVT :: getVectorVT ( Ctx , <STR_LIT> , VT . getVectorNumElements ( ) + 1 ) ;"
LLVM,NVPTX,1156,"else return EVT::getVectorVT(Ctx, <STR_LIT>, VT.getScalarType());"
LLVM,NVPTX,1157,if (STy && STy->isOpaque()) return true;
LLVM,NVPTX,1158,
LLVM,NVPTX,1159,predicted is return true;
LLVM,NVPTX,1160,return true ;
LLVM,NVPTX,1161,return Ops;
LLVM,NVPTX,1162,
LLVM,NVPTX,1163,"return DAG.getTargetGlobalAddress(GV, dl, getPointerTy());"
LLVM,NVPTX,1164,else if ( TheStoreType == MVT :: <STR_LIT> ) {
LLVM,NVPTX,1165,"return DAG . getMergeValues ( Ops , dl ) ;"
LLVM,NVPTX,1166,"SDValue Tmp3 = DAG.getNode(<STR_LIT>, dl, VT, ShOpHi, ExtraShAmt);"
LLVM,NVPTX,1167,"return DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , ShOpHi , RevShAmt ) ;"
LLVM,NVPTX,1168,"SDValue Lo = DAG.getNode(<STR_LIT>, dl, VT, ShOpLo, ShOpHi, ShAmt);"
LLVM,NVPTX,1169,return SDValue ( ) ;
LLVM,NVPTX,1170,"Results.push_back(DAG.getNode(<STR_LIT>, DL, <STR_LIT>, NewLD.getValue(<NUM_LIT>)));"
LLVM,NVPTX,1171,SDValue Res = NewLD.getValue(i);
LLVM,NVPTX,1172,}
LLVM,NVPTX,1173,"return DCI.DAG.getNode(Opc, SDLoc(N), MulType, TruncLHS, TruncRHS);"
LLVM,NVPTX,1174,mallocCode ;
LLVM,NVPTX,1175,for(auto * CU : CUs) delete DwarfARangesSection;
LLVM,NVPTX,1176,
LLVM,NVPTX,1177,"assert((getValueType(DL, Ty) == Outs[OIdx].VT || (getValueType(DL, Ty) == MVT::iPTR) && DL.getPointerTypeSizeInBits(Ty) == MVT::iPTR && Outputs[OIdx].VT == MVT::iPTR), Inconsistent use of valueType and machineValueType);"
LLVM,NVPTX,1178,
LLVM,NVPTX,1179,return NULL.
LLVM,NVPTX,1180,NeedTrunc = true ;
LLVM,NVPTX,1181,"SmallVector<SDValue, i> ScalarRes;"
LLVM,NVPTX,1182,</sAnswer:
LLVM,NVPTX,1183,
LLVM,NVPTX,1184,
LLVM,NVPTX,1185,}
LLVM,NVPTX,1186,}
LLVM,NVPTX,1187,"assert(llvm::getAlign(*(CS->getCalledFunction()), Idx, align));"
LLVM,NVPTX,1188,}
LLVM,NVPTX,1189,O << <STR_LIT> ;
LLVM,NVPTX,1190,"return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ;"
LLVM,NVPTX,1191,return <STR_LIT> ;
LLVM,NVPTX,1192,Info . writeMem = true ;
LLVM,NVPTX,1193,
LLVM,NVPTX,1194,
LLVM,NVPTX,1195,return result;
LLVM,NVPTX,1196,break;
LLVM,NVPTX,1197,"return LowerLOAD ( Op , DAG ) ;"
LLVM,NVPTX,1198,
LLVM,NVPTX,1199,
LLVM,NVPTX,1200,}
LLVM,NVPTX,1201,case <NUM_LIT>: Opcode = <STR_LIT>;
LLVM,NVPTX,1202,
LLVM,NVPTX,1203,
LLVM,NVPTX,1204,
LLVM,NVPTX,1205,return LHSTy.getScalarType().getScalarShiftAmountTy();
LLVM,NVPTX,1206,}
LLVM,NVPTX,1207,Predict the next statement of this code snippet: for (unsigned i = 0;
LLVM,NVPTX,1208,"SDNode *SelectNode = DAG.getSelectCC(dl, Cmp, TrueVal, FalseVal, <STR_LIT>);"
LLVM,NVPTX,1209,"SDValue Hi = DAG.getNode(<STR_LIT>, dl, VT, ShOpLo, ShOpHi, ShAmt);"
LLVM,NVPTX,1210,
LLVM,NVPTX,1211,}
LLVM,NVPTX,1212,"return DAG.getNode(<OPCODE>, SDLoc(N), VT, N0.getOperand(<NUM_LIT>), N0.getOperand(<NUM_LIT>), N1);"
LLVM,NVPTX,1213,
LLVM,NVPTX,1214,}
LLVM,NVPTX,1215,SDValue LoadChain = NewLD.getValue(NumElts+1);
LLVM,NVPTX,1216,Lines 47~54: O << align  << align <<  align  ;
LLVM,NVPTX,1217,
LLVM,NVPTX,1191,return <STR_LIT> ;
LLVM,NVPTX,1192,Info . writeMem = true ;
LLVM,NVPTX,1193,
LLVM,NVPTX,1194,"SDValue result = DAG.getNode(<STR_LIT>, dl, <STR_LIT>, newLD);"
LLVM,NVPTX,1195,"is defining a function called LowerLOADi1, which takes in two parameters: Op (of type SDValue) and DAG (of type SelectionDAG). It then declares a new variable Node which is set to the value of Op's node. The function then casts that node to be a LoadSDNode and the result is stored in a variable called LD. A new variable dl is created of type SDLoc, which is initialized with the value of Node. An assertion is made to check that LD's extension type is equal to a string literal. Another assertion is made to check that Node's value type is equal"
LLVM,NVPTX,1196,
LLVM,NVPTX,1197,"case <STR_LIT>: return LowerEXTRACT_SUBVECTOR(Op, DAG);"
LLVM,NVPTX,1198,"SmallVector < SDValue , <NUM_LIT> > Ops ;"
LLVM,NVPTX,1199,return NewSt ;
LLVM,NVPTX,1200,}
LLVM,NVPTX,1201,"LdResVTs = DAG.getVTList(ListVTs, <NUM_LIT>);"
LLVM,NVPTX,1202,
LLVM,NVPTX,1203,/s> }
LLVM,NVPTX,1204,return MVT::i32;
LLVM,NVPTX,1205,
LLVM,NVPTX,1206,}
LLVM,NVPTX,1207,Predict the next statement of this code snippet: }
LLVM,NVPTX,1208,}
LLVM,NVPTX,1209,}
LLVM,NVPTX,1210,return NewSt ;
LLVM,NVPTX,1211,}
LLVM,NVPTX,1212,
LLVM,NVPTX,1213,
LLVM,NVPTX,1214,
LLVM,NVPTX,1215,
LLVM,NVPTX,1216,FO_idx.O.<STR_LIT> + sz;
LLVM,NVPTX,1217,return <STR_LIT> ;
LLVM,NVPTX,1218,redict: O << <STR_LIT> ;
LLVM,NVPTX,1219,
LLVM,NVPTX,1220,
LLVM,NVPTX,1221,"the beginning of a conditional statement, for example: if (sizesofar <= 10) {"
LLVM,NVPTX,1222,
LLVM,NVPTX,1223,O <<   << getName(*F.getName().str() << uniqueCallSite <<   ;
LLVM,NVPTX,1224,
LLVM,NVPTX,1225,return SDValue ( ) ;
LLVM,NVPTX,1226,"return LowerSTORE ( Op , DAG ) ;"
LLVM,NVPTX,1227,"the case statement <STR_LIT>: return PerformMODCombine (N, DCI, OptLevel);"
LLVM,NVPTX,1228,}
LLVM,NVPTX,1229,opIsLive = true ;
LLVM,NVPTX,1230,}
LLVM,NVPTX,1231,
LLVM,NVPTX,1232,
LLVM,NVPTX,1233,
LLVM,NVPTX,1234,"SDValue newResult = DAG.getNode(<STR_LIT>, dl, Ops);"
LLVM,NVPTX,1235,
LLVM,NVPTX,1236,"case <STR_LIT> : return LowerVSELECT(Op, DAG);"
LLVM,NVPTX,1237,
LLVM,NVPTX,1238,}
LLVM,NVPTX,1239,
LLVM,NVPTX,1240,
LLVM,NVPTX,1241,
LLVM,NVPTX,1242,O << '\\01' ;
LLVM,NVPTX,1243,
LLVM,NVPTX,1244,else return SDValue();
LLVM,NVPTX,1245,
LLVM,NVPTX,1246,O << fail;
LLVM,NVPTX,1247,
LLVM,NVPTX,1248,
LLVM,NVPTX,1249,delete DwarfRangesSection;
LLVM,NVPTX,1250,
LLVM,NVPTX,1251,O << <STR_LIT> << Outs [ OIdx ] . Flags . getByValSize ( ) << <STR_LIT>;
LLVM,NVPTX,1252,if (PTy->getElementType()->isIntegerTy()) {
LLVM,NVPTX,1253,if ( ! STy ) return false;
LLVM,NVPTX,1254,"if ( isa < STR_LIT > ( VTs [ j ] , EVT ) ) {"
LLVM,NVPTX,1255,
LLVM,NVPTX,1256,"case <STR_LIT> : case <STR_LIT> : case <STR_LIT>: followed by several more cases with various <STR_LIT> values, all with the same block of code underneath."
LLVM,NVPTX,1257,if ( numElems > <NUM_LIT> ) {
LLVM,NVPTX,1258,
LLVM,NVPTX,1259,
LLVM,NVPTX,1260,sizesofar += tmpvt . getStoreSizeInBits ( ) ;
LLVM,NVPTX,1261,
LLVM,NVPTX,1262,
LLVM,NVPTX,1263,break ;
LLVM,NVPTX,1264,case <STR_LIT> : break;
LLVM,NVPTX,1265,
LLVM,NVPTX,1266,ScalarRes . push_back ( Res ) ;
LLVM,NVPTX,1267,break;
LLVM,NVPTX,1268,}
LLVM,NVPTX,1269,
LLVM,NVPTX,1270,}
LLVM,NVPTX,1271,default:
LLVM,NVPTX,1272,
LLVM,NVPTX,1273,InVals . push_back ( p ) ;
LLVM,NVPTX,1274,"SDValue p = DAG . getCopyToReg ( Root , dl , ArgGroup , SDValue ( & Inputs [ idx ] , <NUM_LIT> ) ) ;"
LLVM,NVPTX,1275,"DAG.UpdateNodeOperands(Node, Ops);"
LLVM,NVPTX,1276,"SDValue newResult = DAG.getNode(<STR_LIT>, dl, <STR_LIT>, result);"
LLVM,NVPTX,1277,"DAG.ReplaceAllUsesWith(SrcOp, Result);"
LLVM,NVPTX,1278,return Result;
LLVM,NVPTX,1279,"setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ;"
LLVM,NVPTX,1280,
LLVM,NVPTX,1281,O << <STR_LIT> << align << <STR_LIT> ;
LLVM,NVPTX,1282,compared with the return value of MF.getDenormalMode(APFloat::IEEEsingle()).Output == DenormalMode::PreserveSign.
LLVM,NVPTX,1283,
LLVM,NVPTX,1284,
LLVM,NVPTX,1285,"return std :: make_pair ( <NUM_LIT> , <STR_LIT> case 'm' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ;"
LLVM,NVPTX,1286,
LLVM,NVPTX,1287,"SDValue NewSD = DAG.getNode(Opcode, DL, ResVT, LoadChain, BuildVec);"
LLVM,NVPTX,1288,"if ( AddSub ) ScalarRes . push_back ( DAG . getNode ( Opcode , DL , VTList , OtherOpsw , Res ) ) ;"
LLVM,NVPTX,1289,return Chain;
LLVM,NVPTX,1290,break ;
LLVM,NVPTX,1291,
LLVM,NVPTX,1292,SDValue ResChain = DAG.getUNDEF(ValVT);
LLVM,NVPTX,1293,break ;
LLVM,NVPTX,1294,
LLVM,NVPTX,1295,
LLVM,NVPTX,1296,
LLVM,NVPTX,1297,<NUM_LIT + 1>;
LLVM,NVPTX,1298,"Chains.push_back(DAG.getNode(<STR_LIT>, dl, <STR_LIT>, &theChains[1], theChains.size()));"
LLVM,NVPTX,1299,assert (newLD.getNode()->getValueType(1) == MVT::i32);
LLVM,NVPTX,1300,
LLVM,NVPTX,1301,}
LLVM,NVPTX,1302,unsigned PointerSize = ST -> getPointerSize ( ) ;
LLVM,NVPTX,1303,
LLVM,NVPTX,1304,Results.push_back(NewLD.getValue(<NUM_LIT>));
LLVM,NVPTX,1305,
LLVM,NVPTX,1306,
LLVM,NVPTX,1307,
LLVM,NVPTX,1308,
LLVM,NVPTX,1309,
LLVM,NVPTX,1310,O << <STR_LIT> ;
LLVM,NVPTX,1311,sz = DL . getPointerTypeSize ( Ty ) ;
LLVM,NVPTX,1312,
LLVM,NVPTX,1313,}
LLVM,NVPTX,1314,return 0;
LLVM,NVPTX,1315,}
LLVM,NVPTX,1316,`std::string updated_name = *name;
LLVM,NVPTX,1317,
LLVM,NVPTX,1318,if (VT == MVT::i16) {
LLVM,NVPTX,1319,
LLVM,NVPTX,1320,
LLVM,NVPTX,1321,}
LLVM,NVPTX,1322,
LLVM,NVPTX,1323,
LLVM,NVPTX,1324,
LLVM,NVPTX,1325,Builder.SetInsertPoint(OrigBB->getTerminator());
LLVM,NVPTX,1326,LoopBuilder.CreateBr(LoopBB);
LLVM,NVPTX,1327,
LLVM,NVPTX,1328,}
LLVM,NVPTX,1329,AU.addRequired<MemoryDependenceWrapperPass>();
LLVM,NVPTX,1330,AU .addPreserved < LVI > ( ) ;
LLVM,NVPTX,1331,return true;
LLVM,NVPTX,1332,
LLVM,NVPTX,1333,}
LLVM,NVPTX,1334,<DEC_STMT> ;
LLVM,NVPTX,1335,}
LLVM,NVPTX,1336,expandMemSetAsLoop ( Memset ) ;
LLVM,NVPTX,1337,"loopBB -> getTerminator()->addIncoming(newind, loopBB);"
LLVM,NVPTX,1338,
LLVM,NVPTX,1339,
LLVM,NVPTX,1340,MemCpyInst * memcpy = aggrMemcpys [ i ] ;
LLVM,NVPTX,1341,
LLVM,NVPTX,1342,if ( len_int -> getZExtValue ( ) >= MaxAggrCopySize ) {
LLVM,NVPTX,1343,builder.CreateBr(loopBB);
LLVM,NVPTX,1344,"loop . CreateCondBr ( ind , loopBB , loopBB ) ;"
LLVM,NVPTX,1345,loop.CreateBr(contBB);
LLVM,NVPTX,1346,for ( MemSetInst * memsetinst : aggrMemsets ) {
LLVM,NVPTX,1347,
LLVM,NVPTX,1348,if ( ( load -> getPointerOperand ( ) != dstAddr ) || ( store -> getPointerOperand ( ) != srcAddr ) ) continue ;
LLVM,NVPTX,1349,for (LoadInst *LI : AggrLoads) {
LLVM,NVPTX,1350,}
LLVM,NVPTX,1351,
LLVM,NVPTX,1352,
LLVM,NVPTX,1353,
LLVM,NVPTX,1354,
LLVM,NVPTX,1355,"loop.Add(newind, ConstantInt::get(indType, 1));"
LLVM,NVPTX,1356,
LLVM,NVPTX,1357,
LLVM,NVPTX,1358,"LoopBuilder.CreateStore(SetValue, DstAddr) ;"
LLVM,NVPTX,1359,
LLVM,NVPTX,1360,
LLVM,NVPTX,1361,
LLVM,NVPTX,1362,{
LLVM,NVPTX,1363,
LLVM,NVPTX,1364,}
LLVM,NVPTX,1365,"MemCall -> setLength ( ConstantInt :: get ( <BOOL_LIT> , <NUM_LIT> ) ) ;"
LLVM,NVPTX,1366,}
LLVM,NVPTX,1367,return new <ISA_LIT>LowerAllocaPass();
LLVM,NVPTX,1368,
LLVM,NVPTX,1369,Type:  Return nullptr;
LLVM,NVPTX,1370,
LLVM,NVPTX,1371,continue ;
LLVM,NVPTX,1372,
LLVM,NVPTX,1373,
LLVM,NVPTX,1374,
LLVM,NVPTX,1375,
LLVM,NVPTX,1376,
LLVM,NVPTX,1377,"BI -> setOperand ( <NUM_LIT> , NewASCToGeneric ) ;"
LLVM,NVPTX,1378,auto Call = dyn_cast <CallInst>(AllocaUse.getUser());
LLVM,NVPTX,1379,
LLVM,NVPTX,1380,continue ;
LLVM,NVPTX,1381,
LLVM,NVPTX,1382,}
LLVM,NVPTX,1383,}
LLVM,NVPTX,1384,
LLVM,NVPTX,1385,}
LLVM,NVPTX,1386,}
LLVM,NVPTX,1387,return true;
LLVM,NVPTX,1388,
LLVM,NVPTX,1389,
LLVM,NVPTX,1390,
LLVM,NVPTX,1391,"LowerArgs (const <ISA_LIT>TargetMachine * TM = nullptr) : CallGraphSCCPass(ID), TM(TM), MFI(nullptr) {"
LLVM,NVPTX,1392,
LLVM,NVPTX,1393,return isEmbeddedFunction (F) ? runOnEmbeddedFunction (F) : runOnServerFunction (F);
LLVM,NVPTX,1394,return isKernelFunction ( F ) ? runOnKernelFunction ( F ) : runOnDeviceFunction ( F ) ;
LLVM,NVPTX,1395,}
LLVM,NVPTX,1396,AllocA->insertAfter(AllocA);
LLVM,NVPTX,1397,
LLVM,NVPTX,1398,
LLVM,NVPTX,1399,ArgInParam->replaceAllUsesWith(AddrCast);
LLVM,NVPTX,1400,return false ;
LLVM,NVPTX,1401,unsigned AS = DL . getAllocaAddrSpace ( ) ;
LLVM,NVPTX,1402,
LLVM,NVPTX,1403,
LLVM,NVPTX,1404,
LLVM,NVPTX,1405,
LLVM,NVPTX,1406,Type * ValueType = StructType -> getContainedType(0);
LLVM,NVPTX,1407,
LLVM,NVPTX,1408,"within the while loop, where the ItemsToConvert list is being iterated over and each instruction is being cloned in the specified address space. It is possible that the next statement could be the call to the CloneInstInParamAS function or the clone instruction within the llvm::for_each function, depending on the implementation of the functions used."
LLVM,NVPTX,1409,}
LLVM,NVPTX,1410,}
LLVM,NVPTX,1411,
LLVM,NVPTX,1412,
LLVM,NVPTX,1413,
LLVM,NVPTX,1414,"Value * PtrInLocal = new AddrSpaceCastInst(PtrInGeneric, Ptr->getType(), Ptr->getName(), &*InsertPt);"
LLVM,NVPTX,1415,
LLVM,NVPTX,1416,
LLVM,NVPTX,1417,"Value * ArgInGeneric = new AddrSpaceCastInst (ArgInGlobal, Arg->getType(), Arg->getName(), FirstInst);"
LLVM,NVPTX,1418,ArgInGlobal->eraseFromParent();
LLVM,NVPTX,1419,else if ( TM && TM -> getDrvInterface ( ) == <INT_LIT> ) handlePointerParam ( & Arg ) ;
LLVM,NVPTX,1420,
LLVM,NVPTX,1421,}
LLVM,NVPTX,1422,new LowerKernelArgs ( TM ) ;
LLVM,NVPTX,1423,Return Inst->getFirstNonPHI();
LLVM,NVPTX,1424,Value * ArgElem = LI->getOperand(0);
LLVM,NVPTX,1425,an opening curly bracket {
LLVM,NVPTX,1426,LowerKernelArgs (nullptr);
LLVM,NVPTX,1427,
LLVM,NVPTX,1428,
LLVM,NVPTX,1429,
LLVM,NVPTX,1430,: - Variable *SomeVar = new Variable();
LLVM,NVPTX,1431,Function * Return = CvtFunc->getReturnType();
LLVM,NVPTX,1432,
LLVM,NVPTX,1433,
LLVM,NVPTX,1434,<ISA_LIT>ProcessTarget ( Target ) : Return ( StructArgs ) ;
LLVM,NVPTX,1435,lowerStructure(ID);
LLVM,NVPTX,1436,
LLVM,NVPTX,1437,
LLVM,NVPTX,1438,
LLVM,NVPTX,1439,
LLVM,NVPTX,1440,
LLVM,NVPTX,1441,<DV>{
LLVM,NVPTX,1442,CodeAlignDirective = <STR_LIT> ;
LLVM,NVPTX,1443,
LLVM,NVPTX,1444,
LLVM,NVPTX,1445,AsciiDirective = nullptr;
LLVM,NVPTX,1446,Data32bitsDirective = nullptr;
LLVM,NVPTX,1447,
LLVM,NVPTX,1448,
LLVM,NVPTX,1449,
LLVM,NVPTX,1450,CommentString = <STR_LIT> ;
LLVM,NVPTX,1451,DataTypeDirective = <STR_LIT> ;
LLVM,NVPTX,1452,
LLVM,NVPTX,1453,HasDataRegionDirective = true;
LLVM,NVPTX,1454,CodeBlockStart = <STR_LIT> ;
LLVM,NVPTX,1455,UseExternalLibraries = true;
LLVM,NVPTX,1456,ExpectedOutputFormat = AVRO ;
LLVM,NVPTX,1457,Data16bitsDirective = <STR_LIT> ;
LLVM,NVPTX,1458,InlineAsmEnd = <STR_LIT> ;
LLVM,NVPTX,1459,
LLVM,NVPTX,1460,HasSingleParameterDotFile = true ;
LLVM,NVPTX,1461,
LLVM,NVPTX,1462,print hello }
LLVM,NVPTX,1463,return;
LLVM,NVPTX,1464,
LLVM,NVPTX,1465,a conditional statement that checks if the return value of E -> getKind() is equal to MCExpr :: Target and takes appropriate action based on the result.
LLVM,NVPTX,1466,
LLVM,NVPTX,1467,
LLVM,NVPTX,1468,return false;
LLVM,NVPTX,1469,
LLVM,NVPTX,1470,
LLVM,NVPTX,1471,
LLVM,NVPTX,1472,
LLVM,NVPTX,1473,}
LLVM,NVPTX,1474,Kind return _kind ;
LLVM,NVPTX,1475,
LLVM,NVPTX,1476,
LLVM,NVPTX,1477,
LLVM,NVPTX,1478,
LLVM,NVPTX,1479,return this->Flt;
LLVM,NVPTX,1480,return SymExpr;
LLVM,NVPTX,1481,
LLVM,NVPTX,1482,"return new <ISA_LIT>GenericMCSymbolRefExpr ( SymExpr , Ctx );"
LLVM,NVPTX,1483,return nullptr;
LLVM,NVPTX,1484,
LLVM,NVPTX,1485,__isa));
LLVM,NVPTX,1486,
LLVM,NVPTX,1487,
LLVM,NVPTX,1488,}
LLVM,NVPTX,1489,
LLVM,NVPTX,1490,
LLVM,NVPTX,1491,return new (Flt);
LLVM,NVPTX,1492,}
LLVM,NVPTX,1493,
LLVM,NVPTX,1494,}
LLVM,NVPTX,1495,
LLVM,NVPTX,1496,if (HexStr.length() >= NumHex) {
LLVM,NVPTX,1497,
LLVM,NVPTX,1498,
LLVM,NVPTX,1499,
LLVM,NVPTX,1500,
LLVM,NVPTX,1501,}
LLVM,NVPTX,1502,
LLVM,NVPTX,1503,
LLVM,NVPTX,1505,return SP_NewThis}
LLVM,NVPTX,1506,OS << HexStr ;
LLVM,NVPTX,1507,OS << converting to double precision float;
LLVM,NVPTX,1508,"return new <ISA_LIT>MCInstPrinter(T, SyntaxVariant, MAI, MII, MRI);"
LLVM,NVPTX,1509,}
LLVM,NVPTX,1510,return X;
LLVM,NVPTX,1511,<e> Initialise Register Info for ISA X with number count <NUM_LIT> ;
LLVM,NVPTX,1512,{
LLVM,NVPTX,1513,
LLVM,NVPTX,1514,"TargetRegistry::RegisterAsmTargetStreamer(*T, createTargetAsmStreamer);"
LLVM,NVPTX,1515,"TargetRegistry::RegisterAsmPrinter(*T, create<ISA_LIT>AsmPrinter);"
LLVM,NVPTX,1516,X->getNumRegs();
LLVM,NVPTX,1517,X->InitMCRegisterInfo();
LLVM,NVPTX,1518,"TargetRegistry :: RegisterMCSubtargetInfo ( * T , create<ISA_LIT>MCSubtargetInfo ) ;"
LLVM,NVPTX,1519,
LLVM,NVPTX,1520,X -> setTargetCpu ( TT ) ;
LLVM,NVPTX,1521,return <NUM_LIT> ;
LLVM,NVPTX,1522,"return new ISA_LITMCInstPrinter(T, SyntaxVariant, MAI, MII, MRI, STI);"
LLVM,NVPTX,1523,"TargetRegistry :: RegisterMCAsmBackend ( * T , create<ISA_LIT>MCAsmBackend ) ;"
LLVM,NVPTX,1524,"TargetRegistry :: RegisterMCRelocationInfo ( * T , create<ISA_LIT>MCRelocationInfo ) ;"
LLVM,NVPTX,1525,return X;
LLVM,NVPTX,1526,
LLVM,NVPTX,1527,"TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>Target64 , create<ISA_LIT>MCRegisterInfo ) ;"
LLVM,NVPTX,1528,"TargetRegistry :: RegisterMCInstPrinter (The<ISA_LIT>Target64, create<ISA_LIT>MCInstPrinter);"
LLVM,NVPTX,1529,
LLVM,NVPTX,1530,if (SyntaxVariant == 1) {
LLVM,NVPTX,1531,
LLVM,NVPTX,1532,}
LLVM,NVPTX,1533,
LLVM,NVPTX,1534,
LLVM,NVPTX,1535,
LLVM,NVPTX,1536,This Macro builds a MCSubtargetInfo object configured for the specified processor in the given Triple string. }
LLVM,NVPTX,1537,"TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>Target32 , create<ISA_LIT>SubtargetInfo ) ;"
LLVM,NVPTX,1538,const MachineBasicBlock *PrevMBB = Prev.getParent();
LLVM,NVPTX,1539,
LLVM,NVPTX,1540,
LLVM,NVPTX,1541,}
LLVM,NVPTX,1542,auto Reg = MRI . createVirtualRegister ( MVT :: i32 ) ;
LLVM,NVPTX,1543,
LLVM,NVPTX,1544,}
LLVM,NVPTX,1545,auto & MBB = * MBB . end();
LLVM,NVPTX,1546,
LLVM,NVPTX,1547,
LLVM,NVPTX,1548,.getRegisterInfo ( ) ;
LLVM,NVPTX,1549,
LLVM,NVPTX,1550,
LLVM,NVPTX,1551,if (MRI.hasOneNonDBGUse(Prev.getOperand(<NUM_LIT>).getReg())) {
LLVM,NVPTX,1552,"MIB = BuildMI ( MF , Root . getDebugLoc ( ) , TII -> get ( Prev . getOpcode ( ) ) , Root . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( NRI -> getFrameLocalRegister ( MF ) ) . add ( Root . getOperand ( <NUM_LIT> ) ) ;"
LLVM,NVPTX,1553,}
LLVM,NVPTX,1554,throw new Error(Cannot instantiate class Peephole);
LLVM,NVPTX,1555,
LLVM,NVPTX,1556,
LLVM,NVPTX,1557,
LLVM,NVPTX,1558,}
LLVM,NVPTX,1559,
LLVM,NVPTX,1560,MI.removeFromParent ( ) ;
LLVM,NVPTX,1561,}
LLVM,NVPTX,1562,"MaxAlign = std :: max ( Align , MaxAlign ) ;"
LLVM,NVPTX,1563,
LLVM,NVPTX,1564,}
LLVM,NVPTX,1565,m_TSCI ( ) : TargetTransformInfo ( & ) {
LLVM,NVPTX,1566,return ID + 1;
LLVM,NVPTX,1567,
LLVM,NVPTX,1568,"MFI . setObjectOffset ( FrameIdx , Offset ) ;"
LLVM,NVPTX,1569,}
LLVM,NVPTX,1570,
LLVM,NVPTX,1571,
LLVM,NVPTX,1572,
LLVM,NVPTX,1573,}
LLVM,NVPTX,1574,
LLVM,NVPTX,1575,if (!TFI.targetHandlesStackFrameRounding() ) {
LLVM,NVPTX,1576,
LLVM,NVPTX,1577,"NewMaxAlign = std::max(MaxAlign, Alignment);"
LLVM,NVPTX,1578,"MI.getDebugExpression().prepend(DIExpression::ApplyOffset, Offset);"
LLVM,NVPTX,1579,}
LLVM,NVPTX,1580,}
LLVM,NVPTX,1581,Modified = true ;
LLVM,NVPTX,1582,}
LLVM,NVPTX,1583,}
LLVM,NVPTX,1584,
LLVM,NVPTX,1585,Modified = true ;
LLVM,NVPTX,1586,
LLVM,NVPTX,1587,MFI.setLocalFrameObjectAllocationBlockOffset(Offset);
LLVM,NVPTX,1588,}
LLVM,NVPTX,1589,"std :: pair <<STR_LIT> , bool >"
LLVM,NVPTX,1590,"DIExpr = DIExpression :: append ( DIExpr , DIExpression :: Piece ) Ops.push_back(Offset);"
LLVM,NVPTX,1591,Offset = MFI->getLocalFrameSize();
LLVM,NVPTX,1592,
LLVM,NVPTX,1593,}
LLVM,NVPTX,1594,
LLVM,NVPTX,1595,The next statement could potentially be an end or closing statement to complete the function or code block. For example: end function or }
LLVM,NVPTX,1596,PassManager PM;
LLVM,NVPTX,1597,
LLVM,NVPTX,1598,}
LLVM,NVPTX,1599,
LLVM,NVPTX,1600,
LLVM,NVPTX,1601,
LLVM,NVPTX,1602,
LLVM,NVPTX,1603,
LLVM,NVPTX,1604,int Offset2 = MF . getFrameInfo ( ) . getObjectOffset ( FrameIndex ) + MI . getOperand ( FIOperandNum + 1 ) . getImm ( ) ;
LLVM,NVPTX,1605,return <STR_LIT> ;
LLVM,NVPTX,1606,return <STR_LIT> ;
LLVM,NVPTX,1607,
LLVM,NVPTX,1608,if ( RC == & <STR_LIT> ) return <STR_LIT> ;
LLVM,NVPTX,1609,
LLVM,NVPTX,1610,
LLVM,NVPTX,1611,
LLVM,NVPTX,1612,return CalleeSavedRegClasses;
LLVM,NVPTX,1613,return CalleeSavedRegs ;
LLVM,NVPTX,1614,
LLVM,NVPTX,1615,}
LLVM,NVPTX,1616,}
LLVM,NVPTX,1617,return <STR_LIT> ;
LLVM,NVPTX,1618,
LLVM,NVPTX,1619,
LLVM,NVPTX,1620,"<ISA_LIT>RegisterInfo :: <ISA_LIT>RegisterInfo ( const TargetRegisterInfo & tri ) : <ISA_LIT>GenRegisterInfo ( <NUM_LIT> ) , Is64Bit ( tri . is64Bit ( ) )"
LLVM,NVPTX,1621,MF.getFrameInfo()->getObjectOffset(FrameIndex) + MI.getOperand(FIOperandNum + <NUM_LIT> - 1).getImm();
LLVM,NVPTX,1622,
LLVM,NVPTX,1623,
LLVM,NVPTX,1624,}
LLVM,NVPTX,1625,}
LLVM,NVPTX,1626,return <STR_LIT> ;
LLVM,NVPTX,1627,return <STR_LIT> ;
LLVM,NVPTX,1628,
LLVM,NVPTX,1629,"MI . getOperand ( FIOperandNum ) . ChangeToRegister ( <STR_LIT> , false ) ;"
LLVM,NVPTX,1630,}
LLVM,NVPTX,1631,
LLVM,NVPTX,1632,
LLVM,NVPTX,1633,}
LLVM,NVPTX,1634,
LLVM,NVPTX,1635,
LLVM,NVPTX,1636,this . Is64Bit = st . is64Bit ( ) ;
LLVM,NVPTX,1637,return CalleeSavedRegClasses;
LLVM,NVPTX,1638,return MBB.end();
LLVM,NVPTX,1639,MI.getOperand(i + 2).getImm();
LLVM,NVPTX,1640,"getOffset (PointedToOperand & PtrOp, <ZERO_LIT> BlockSize) const {"
LLVM,NVPTX,1641,
LLVM,NVPTX,1642,
LLVM,NVPTX,1643,
LLVM,NVPTX,1644,}
LLVM,NVPTX,1645,<STR_LIT> ;
LLVM,NVPTX,1646,llvm_unreachable ( <STR_LIT> ) ;
LLVM,NVPTX,1647,
LLVM,NVPTX,1648,return <STR_LIT> ;
LLVM,NVPTX,1649,
LLVM,NVPTX,1650,
LLVM,NVPTX,1651,TM.initializeSubtargetInfo(*this);
LLVM,NVPTX,1652,
LLVM,NVPTX,1653,MF.emit(code);
LLVM,NVPTX,1654,return TM.getRegisterInfo()->getFrameRegister(MF);
LLVM,NVPTX,1655,
LLVM,NVPTX,1656,
LLVM,NVPTX,1657,
LLVM,NVPTX,1658,
LLVM,NVPTX,1659,"<ISA_LIT>RegisterInfo ::<ISA_LIT>RegisterInfo ( ) :<ISA_LIT>GenRegisterInfo ( <NUM_LIT> ),<S> {"
LLVM,NVPTX,1660,
LLVM,NVPTX,1661,case <STR_LIT> : MachineOperand & ImageHandle = MI . getOperand ( <NUM_LIT> ) ;
LLVM,NVPTX,1662,
LLVM,NVPTX,1663,}
LLVM,NVPTX,1664,return <STR_LIT> ;
LLVM,NVPTX,1665,
LLVM,NVPTX,1666,return Changed;
LLVM,NVPTX,1667,return Changed ;
LLVM,NVPTX,1668,"MF . getOrCreateGlobalValue ( Sym . str ( ) , <NULL LIT> ) ;"
LLVM,NVPTX,1669,Idx = MFI -> getImageHandleSymbolIndex ( GV -> getName ( ) . data ( ) ) ;
LLVM,NVPTX,1670,
LLVM,NVPTX,1671,Changed |= processInstr ( MI ) ;
LLVM,NVPTX,1672,
LLVM,NVPTX,1673,}
LLVM,NVPTX,1674,}
LLVM,NVPTX,1675,;
LLVM,NVPTX,1676,return PassName;
LLVM,NVPTX,1677,
LLVM,NVPTX,1678,
LLVM,NVPTX,1679,return true ;
LLVM,NVPTX,1680,<Send> <Self> ::receiveImage(<ArgumentIndex> => x is an <IMAGE_LIT>
LLVM,NVPTX,1681,The next statement could possibly be something along the lines of: Idx = 0;
LLVM,NVPTX,1682,if (I->isReturn()) return;
LLVM,NVPTX,1683,
LLVM,NVPTX,1684,return this;
LLVM,NVPTX,1685,"PrintNextSwitchToSection(MAI, T, OS, Subsection);"
LLVM,NVPTX,1686,
LLVM,NVPTX,1687,return true;
LLVM,NVPTX,1688,return true;
LLVM,NVPTX,1689,
LLVM,NVPTX,1690,
LLVM,NVPTX,1691,
LLVM,NVPTX,1692,
LLVM,NVPTX,1693,SAC( ) }
LLVM,NVPTX,1694,
LLVM,NVPTX,1695,
LLVM,NVPTX,1696,"defines a function called PrintSwitchToSection that takes in three arguments: MAI, OS, and Subsection."
LLVM,NVPTX,1697,
LLVM,NVPTX,1698,
LLVM,NVPTX,1699,
LLVM,NVPTX,1700,"for the return statement, followed by a semicolon. So it could be something like: return Hello World!;"
LLVM,NVPTX,1701,
LLVM,NVPTX,1702,
LLVM,NVPTX,1703,}
LLVM,NVPTX,1704,"return MCSection(V, K);"
LLVM,NVPTX,1705,
LLVM,NVPTX,1706,{
LLVM,NVPTX,1707,
LLVM,NVPTX,1708,
LLVM,NVPTX,1709,
LLVM,NVPTX,1710,
LLVM,NVPTX,1711,
LLVM,NVPTX,1712,AU.addPreserved<MachineLoopInfo>() ;
LLVM,NVPTX,1713,
LLVM,NVPTX,1714,AU . addRequired < AliasAnalysis > ( ) ;
LLVM,NVPTX,1715,}
LLVM,NVPTX,1716,}
LLVM,NVPTX,1717,
LLVM,NVPTX,1718,}
LLVM,NVPTX,1719,print Running FP16 math. if hasFP16Math() && !NoF16Math;
LLVM,NVPTX,1720,
LLVM,NVPTX,1721,
LLVM,NVPTX,1722,
LLVM,NVPTX,1723,
LLVM,NVPTX,1724,return;
LLVM,NVPTX,1725,}
LLVM,NVPTX,1726,return m_targetFrameLowering;
LLVM,NVPTX,1727,}
LLVM,NVPTX,1728,
LLVM,NVPTX,1729,"A potential next statement for this code snippet could be a return statement, which would end the function and possibly return a value or object. For example: return DAGInfo;"
LLVM,NVPTX,1730,return m_smVersion;
LLVM,NVPTX,1731,
LLVM,NVPTX,1732,
LLVM,NVPTX,1733,}
LLVM,NVPTX,1734,}
LLVM,NVPTX,1735,return SmVersion >= <NUM_LIT>+1;
LLVM,NVPTX,1736,return SmVersion >= 32;
LLVM,NVPTX,1737,throw Error;
LLVM,NVPTX,1738,
LLVM,NVPTX,1739,return SmVersion >= 1;
LLVM,NVPTX,1740,
LLVM,NVPTX,1741,
LLVM,NVPTX,1742,Syntax error: Missing DOT_OPERATOR after SmVersion >= <NUM_LIT>
LLVM,NVPTX,1743,
LLVM,NVPTX,1744,
LLVM,NVPTX,1745,bool exitFlag1 = false ;
LLVM,NVPTX,1746,return std::isinf(1.0);
LLVM,NVPTX,1747,
LLVM,NVPTX,1748,
LLVM,NVPTX,1749,
LLVM,NVPTX,1750,
LLVM,NVPTX,1751,
LLVM,NVPTX,1752,return _rot64 != nullptr;
LLVM,NVPTX,1753,
LLVM,NVPTX,1754,double hasSWROT32() const {
LLVM,NVPTX,1755,
LLVM,NVPTX,1756,PTXVersion = <NUM_LIT>;
LLVM,NVPTX,1757,
LLVM,NVPTX,1758,
LLVM,NVPTX,1759,
LLVM,NVPTX,1760,
LLVM,NVPTX,1761,
LLVM,NVPTX,1762,
LLVM,NVPTX,1763,}
LLVM,NVPTX,1764,
LLVM,NVPTX,1765,
LLVM,NVPTX,1766,
LLVM,NVPTX,1767,
LLVM,NVPTX,1768,return HasAtomScope;
LLVM,NVPTX,1769,
LLVM,NVPTX,1770,
LLVM,NVPTX,1771,
LLVM,NVPTX,1772,
LLVM,NVPTX,1773,The next statement may be a conditional statement checking that the variable p is not null and then performing some action based on that condition. It might look something like: ```if (p != null) {
LLVM,NVPTX,1774,
LLVM,NVPTX,1775,"strcpy ( Attr . Arch , TargetName . c_str ( ) ) ;"
LLVM,NVPTX,1776,else if (CPU.empty()) {
LLVM,NVPTX,1777,
LLVM,NVPTX,1778,
LLVM,NVPTX,1779,
LLVM,NVPTX,1780,
LLVM,NVPTX,1781,
LLVM,NVPTX,1782,
LLVM,NVPTX,1783,
LLVM,NVPTX,1784,
LLVM,NVPTX,1785,return IsConditionMet;
LLVM,NVPTX,1786,
LLVM,NVPTX,1787,return hasFP16Math;
LLVM,NVPTX,1788,
LLVM,NVPTX,1789,
LLVM,NVPTX,1790,if ( PTXVersion == <NUM_LIT> ) {
LLVM,NVPTX,1791,
LLVM,NVPTX,1792,}
LLVM,NVPTX,1793,
LLVM,NVPTX,1794,
LLVM,NVPTX,1795,
LLVM,NVPTX,1796,setOptions(T);
LLVM,NVPTX,1797,
LLVM,NVPTX,1798,
LLVM,NVPTX,1799,
LLVM,NVPTX,1800,
LLVM,NVPTX,1801,
LLVM,NVPTX,1802,
LLVM,NVPTX,1803,
LLVM,NVPTX,1804,
LLVM,NVPTX,1805,
LLVM,NVPTX,1806,
LLVM,NVPTX,1807,
LLVM,NVPTX,1808,
LLVM,NVPTX,1809,
LLVM,NVPTX,1810,}
LLVM,NVPTX,1811,
LLVM,NVPTX,1812,
LLVM,NVPTX,1813,}
LLVM,NVPTX,1814,"Set up target registration for 'Triple :: nvptx64' with Y as the target identifier, 'getThe<ISA_LIT>Target64()' as the target creation function, and <STR_LIT> and <STR_LIT> as the target description strings."
LLVM,NVPTX,1815,"RegisterTarget < Triple :: x86 > Z ( getThe<ISA_LIT>TargetX86 ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ;"
LLVM,NVPTX,1816,
LLVM,NVPTX,1817,"a RegisterTarget < Triple :: nvptx > Y ( The<ISA_LIT>Target64 , <STR_LIT> , <STR_LIT> ) ;"
LLVM,NVPTX,1818,
LLVM,NVPTX,1819,addPass ( createDeadCodeEliminationPass ( ) ) ;
LLVM,NVPTX,1820,}
LLVM,NVPTX,1821,
LLVM,NVPTX,1822,removePass ( & PostInlineMachineSinkingID ) ;
LLVM,NVPTX,1823,
LLVM,NVPTX,1824,addPass ( & RegisterCoalescerID ) ;
LLVM,NVPTX,1825,addPass ( create<ISA_SSAPass> ( ) ) ;
LLVM,NVPTX,1826,addPass ( create<InstructionCombining>Pass ( ) ) ;
LLVM,NVPTX,1827,addPass ( create<ISA_RED>ProxyRegErasurePass ( ) ) ;
LLVM,NVPTX,1828,
LLVM,NVPTX,1829,}
LLVM,NVPTX,1830,
LLVM,NVPTX,1831,
LLVM,NVPTX,1832,addPass ( createSparseConditionalConstantPropagationPass ( ) ) ;
LLVM,NVPTX,1833,PM . add ( createEarly <ISA_LIT>Instrumentation Pass ( & <ISA_LIT> ));
LLVM,NVPTX,1834,if (is64Bit && UseShortPointers) {
LLVM,NVPTX,1835,
LLVM,NVPTX,1836,
LLVM,NVPTX,1837,
LLVM,NVPTX,1838,}
LLVM,NVPTX,1839,initialize<ISA_LIT>LowerGlobalPass ( PR ) ;
LLVM,NVPTX,1840,<ISA_LIT>PassManagerBuilder builder ;
LLVM,NVPTX,1841,
LLVM,NVPTX,1842,
LLVM,NVPTX,1843,
LLVM,NVPTX,1844,
LLVM,NVPTX,1845,
LLVM,NVPTX,1846,
LLVM,NVPTX,1847,throw logic_error(addEarlyCSEOrGVNPass is not implemented yet);
LLVM,NVPTX,1848,
LLVM,NVPTX,1849,addFastScheduling ( RegAllocPass ) ;
LLVM,NVPTX,1850,
LLVM,NVPTX,1851,
LLVM,NVPTX,1852,addPass ( createPostOrderFunctionAttrsPass ( ) ) ;
LLVM,NVPTX,1853,printAndVerify ( <STR_LIT> ) ;
LLVM,NVPTX,1854,addPass ( & MachineSchedulerID ) ;
LLVM,NVPTX,1855,
LLVM,NVPTX,1856,
LLVM,NVPTX,1857,"The next statement could potentially be the closing curly brace, }"
LLVM,NVPTX,1858,<MACHINE_LIT>TargetMachine64 :: finalize
LLVM,NVPTX,1859,return PassConfig;
LLVM,NVPTX,1860,
LLVM,NVPTX,1861,
LLVM,NVPTX,1862,
LLVM,NVPTX,1863,
LLVM,NVPTX,1864,}
LLVM,NVPTX,1865,initialize<ISA_LIT>LowerGlobalsPass(PR);
LLVM,NVPTX,1866,
LLVM,NVPTX,1867,
LLVM,NVPTX,1868,
LLVM,NVPTX,1869,
LLVM,NVPTX,1870,
LLVM,NVPTX,1871,return true;
LLVM,NVPTX,1872,
LLVM,NVPTX,1873,ISA_LIT>TargetMachine :: ~ <ISA_LIT>TargetMachine ( ) {
LLVM,NVPTX,1874,
LLVM,NVPTX,1875,}
LLVM,NVPTX,1876,}
LLVM,NVPTX,1877,
LLVM,NVPTX,1878,
LLVM,NVPTX,1879,
LLVM,NVPTX,1880,
LLVM,NVPTX,1881,
LLVM,NVPTX,1882,
LLVM,NVPTX,1883,"<ISA_LIT>TargetMachine32(T, TT, CPU, FS, Options, RM, CM, OL);"
LLVM,NVPTX,1884,
LLVM,NVPTX,1885,
LLVM,NVPTX,1886,
LLVM,NVPTX,1887,addPass ( createLoopRotatePass ( ) ) ;
LLVM,NVPTX,1888,}
LLVM,NVPTX,1889,
LLVM,NVPTX,1890,}
LLVM,NVPTX,1891,Return true;
LLVM,NVPTX,1892,PM.run();
LLVM,NVPTX,1893,initialize<ISA_LIT>OptimizeVectorPass ( PR ) ;
LLVM,NVPTX,1894,
LLVM,NVPTX,1895,
LLVM,NVPTX,1896,return isa<TargetMachine64>(T);
LLVM,NVPTX,1897,
LLVM,NVPTX,1898,
LLVM,NVPTX,1899,an opening bracket ({
LLVM,NVPTX,1900,
LLVM,NVPTX,1901,
LLVM,NVPTX,1902,
LLVM,NVPTX,1903,
LLVM,NVPTX,1904,error: 'FrameLowering' was not declared in this scope
LLVM,NVPTX,1905,
LLVM,NVPTX,1906,}
LLVM,NVPTX,1907,
LLVM,NVPTX,1908,
LLVM,NVPTX,1909,return &ManagedStrPool;
LLVM,NVPTX,1910,"return std :: make_pair ( II -> getArgOperand ( <NUM_LIT> ) , llvm :: ADDRESS_SPACE_PRIVATE ) ;"
LLVM,NVPTX,1911,
LLVM,NVPTX,1912,
LLVM,NVPTX,1913,
LLVM,NVPTX,1914,
LLVM,NVPTX,1915,return subtarget;
LLVM,NVPTX,1916,return subtarget;
LLVM,NVPTX,1917,
LLVM,NVPTX,1918,
LLVM,NVPTX,1919,}
LLVM,NVPTX,1920,addPass ( createModuleCleanupPass ( ) ) ;
LLVM,NVPTX,1921,addPass ( createLowerSwitchPass ( ) ) ;
LLVM,NVPTX,1922,
LLVM,NVPTX,1923,
LLVM,NVPTX,1924,return false;
LLVM,NVPTX,1925,"return new <ISA_LIT>TargetPassConfig(this, PM);"
LLVM,NVPTX,1926,
LLVM,NVPTX,1927,
LLVM,NVPTX,1928,initialize<ISA_LIT>LowerVectorPass ( PR );
LLVM,NVPTX,1929,return false;
LLVM,NVPTX,1930,
LLVM,NVPTX,1931,return CodeModel :: getN
LLVM,NVPTX,1932,
LLVM,NVPTX,1933,
LLVM,NVPTX,1934,"runPasses ( MFunction, PredicateC, PostProPredicates ) ;"
LLVM,NVPTX,1935,}
LLVM,NVPTX,1936,}
LLVM,NVPTX,1937,initializeNVVMPrintModulePass ( * PassRegistry :: getPassRegistry ( ) ) ;
LLVM,NVPTX,1938,}
LLVM,NVPTX,1939,
LLVM,NVPTX,1940,return TargetLowering;
LLVM,NVPTX,1941,addPass(createMachineCodeAnalysis());
LLVM,NVPTX,1942,addPass ( createUnrollLoopPass ( ) ) ;
LLVM,NVPTX,1943,
LLVM,NVPTX,1944,
LLVM,NVPTX,1945,
LLVM,NVPTX,1946,
LLVM,NVPTX,1947,
LLVM,NVPTX,1948,
LLVM,NVPTX,1949,
LLVM,NVPTX,1950,
LLVM,NVPTX,1951,addPass( create<ISA_LIT>LowerGlobalOpPass() );
LLVM,NVPTX,1952,return false;
LLVM,NVPTX,1953,
LLVM,NVPTX,1954,initialize<ISA_LIT>FinalizePass ( PR ) ;
LLVM,NVPTX,1955,
LLVM,NVPTX,1956,addPass (create<ISA_LIT>PrintAnalysisPass());
LLVM,NVPTX,1957,Ret += <STR_LIT> ;
LLVM,NVPTX,1958,createGenericToNVVMPass();
LLVM,NVPTX,1959,addPass ( createEarlyCSEPass ( ) ) ;
LLVM,NVPTX,1960,
LLVM,NVPTX,1961,
LLVM,NVPTX,1962,
LLVM,NVPTX,1963,
LLVM,NVPTX,1964,
LLVM,NVPTX,1965,initialize<ISA_LIT>LowerGlobalAllocPass ( * PassRegistry :: getPassRegistry ( ) ) ;
LLVM,NVPTX,1966,addPass ( create<ISA_LIT>AddressSpaceAliasAnalysis ( ) ) ;
LLVM,NVPTX,1967,
LLVM,NVPTX,1968,initialize<ISA_LIT>LowerBitSetsPass ( PR ) ;
LLVM,NVPTX,1969,initialize <ISA_LIT>LowerGlobalToLocalPass ( PR ) ;
LLVM,NVPTX,1970,}
LLVM,NVPTX,1971,initializeAsmPrinterPass(* PassRegistry::getPassRegistry());
LLVM,NVPTX,1972,
LLVM,NVPTX,1973,
LLVM,NVPTX,1974,disablePass ( & TargetIndependentCodeInserterID ) ;
LLVM,NVPTX,1975,<INT_LIT> }
LLVM,NVPTX,1976,
LLVM,NVPTX,1977,
LLVM,NVPTX,1978,
LLVM,NVPTX,1979,
LLVM,NVPTX,1980,
LLVM,NVPTX,1981,initialize<ISA_LIT>TailMergingPass ( * PassRegistry :: getPassRegistry ( ) ) ;
LLVM,NVPTX,1982,}
LLVM,NVPTX,1983,
LLVM,NVPTX,1984,
LLVM,NVPTX,1985,
LLVM,NVPTX,1986,}
LLVM,NVPTX,1987,
LLVM,NVPTX,1988,}
LLVM,NVPTX,1989,
LLVM,NVPTX,1990,
LLVM,NVPTX,1991,
LLVM,NVPTX,1992,
LLVM,NVPTX,1993,initialize<ISA_LIT>EraseUnusedFunctionsPass ( * PassRegistry :: getPassRegistry ( ) ) ;
LLVM,NVPTX,1994,TargetPassConfig::addIRPasses();
LLVM,NVPTX,1995,disablePass ( & MachineCopyPropagationID ) ;
LLVM,NVPTX,1996,probably going to be addPass ( create<ISA_LIT>DeadStoreEliminationPass ( ) ) ;
LLVM,NVPTX,1997,addPass ( create<ISA_LIT>VectorFunctionSelectionPass ( ) ) ;
LLVM,NVPTX,1998,addPass( create<ISA_LIT>ReloadForPassesPass() );
LLVM,NVPTX,1999,}
LLVM,NVPTX,2000,addPass (createNVVMReflectPass(ST.getSmVersion()));
LLVM,NVPTX,2001,addPass ( create<ISA_LIT>EntryPointPass ( ) ) ;
LLVM,NVPTX,2002,initialize<ISA_LIT>DeadCodeEliminationPass ( PR ) ;
LLVM,NVPTX,2003,}
LLVM,NVPTX,2004,addPass (createNVVMMetadataPass(ST.getSmVersion())) ;
LLVM,NVPTX,2005,
LLVM,NVPTX,2006,disablePass ( & NVVMReflectPassID );
LLVM,NVPTX,2007,addPass(createGenericTypeOutputPass());
LLVM,NVPTX,2008,addPass ( createPrintModulePass ( ... ) ) ;
LLVM,NVPTX,2009,addPass ( create<ISA_LIT>AMDGPUCFGStructurizerPass ( ) ) ;
LLVM,NVPTX,2010,
LLVM,NVPTX,2011,return false;
LLVM,NVPTX,2012,}
LLVM,NVPTX,2013,return getSubtargetImpl()->getIntrinsicInfo();
LLVM,NVPTX,2014,
LLVM,NVPTX,2015,<CODE_LIT> InstrInfo * getInstrInfo ( ) const override ;
LLVM,NVPTX,2016,
LLVM,NVPTX,2017,
LLVM,NVPTX,2018,
LLVM,NVPTX,2019,
LLVM,NVPTX,2020,
LLVM,NVPTX,2021,return &Subtarget;
LLVM,NVPTX,2022,
LLVM,NVPTX,2023,
LLVM,NVPTX,2024,TargetLowering *getTargetLowering() const {
LLVM,NVPTX,2025,"DwarfLocSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ;"
LLVM,NVPTX,2026,
LLVM,NVPTX,2027,
LLVM,NVPTX,2028,}
LLVM,NVPTX,2029,return nullptr;
LLVM,NVPTX,2030,return MCSection::getReadOnly();
LLVM,NVPTX,2031,
LLVM,NVPTX,2032,
LLVM,NVPTX,2033,return new TargetObjectFile();
LLVM,NVPTX,2034,return true;
LLVM,NVPTX,2035,"DwarfDebugStrSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ;"
LLVM,NVPTX,2036,
LLVM,NVPTX,2037,
LLVM,NVPTX,2038,"return dyn_cast_or_null<MCSection>(SectionForGlobal<GlobalObject>(GO, SectionOf<C>(C, Align)));"
LLVM,NVPTX,2039,}
LLVM,NVPTX,2040,"DebugSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getDebug ( ) ) ;"
LLVM,NVPTX,2041,}
LLVM,NVPTX,2042,}
LLVM,NVPTX,2043,"DwarfRangesSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ;"
LLVM,NVPTX,2044,
LLVM,NVPTX,2045,
LLVM,NVPTX,2046,
LLVM,NVPTX,2047,Delete DwarfStrSection ;
LLVM,NVPTX,2048,
LLVM,NVPTX,2049,}
LLVM,NVPTX,2050,}
LLVM,NVPTX,2051,"overrides the getExplicitSectionGlobal function and specifies that it takes in four parameters: GV, Kind, Mang, and TM. It then returns a MCSection pointer."
LLVM,NVPTX,2052,}
LLVM,NVPTX,2053,}
LLVM,NVPTX,2054,RelocationTableSection = nullptr ;
LLVM,NVPTX,2055,'OS << <STR_LIT> ;
LLVM,NVPTX,2056,if (Section == <STR_LIT>) {
LLVM,NVPTX,2057,
LLVM,NVPTX,2058,s> DwarfFiles.emplace_back(Directive);
LLVM,NVPTX,2059,}
LLVM,NVPTX,2060,if (Section == FI -> getDwarfGnuPubTypesSection ()) return true;
LLVM,NVPTX,2061,}
LLVM,NVPTX,2062,S.EmitLabel ( nullptr ) }
LLVM,NVPTX,2063,
LLVM,NVPTX,2064,getStreamer().EmitRawText(S.data());
LLVM,NVPTX,2065,"FI->printSection(OS, *getStreamer().getContext().getAsmInfo(), FI->getTargetTriple(), Section, Subsection);"
LLVM,NVPTX,2066,"Section->PrintSwitchToSection(*getStreamer().getContext().getAsmInfo(), FI->getTargetTriple(), OS, SubSection);"
LLVM,NVPTX,2067,assert ( ! CurSection && <STR_LIT> ) ;
LLVM,NVPTX,2068,}
LLVM,NVPTX,2069,
LLVM,NVPTX,2070,
LLVM,NVPTX,2071,64;
LLVM,NVPTX,2072,(unsigned J = 0;
LLVM,NVPTX,2073,}
LLVM,NVPTX,2074,
LLVM,NVPTX,2075,
LLVM,NVPTX,2076,OS << * It ;
LLVM,NVPTX,2077,It != End ;
LLVM,NVPTX,2078,return 0;
LLVM,NVPTX,2079,}
LLVM,NVPTX,2080,
LLVM,NVPTX,2081,
LLVM,NVPTX,2082,
LLVM,NVPTX,2083,}
LLVM,NVPTX,2084,
LLVM,NVPTX,2085,if (ChainSizeInBytes <= Alignment) {
LLVM,NVPTX,2086,return Alignment * AddrSpace >= ChainSizeInBytes;
LLVM,NVPTX,2087,
LLVM,NVPTX,2088,return BaseT::getArithmeticInstrCost as in the default case.
LLVM,NVPTX,2089,
LLVM,NVPTX,2090,K.getSizeInBits();
LLVM,NVPTX,2091,UP . Debug = false ;
LLVM,NVPTX,2092,if (I) {
LLVM,NVPTX,2093,return SimplifiedSpecialCase;
LLVM,NVPTX,2094,then perform an action based on these values.
LLVM,NVPTX,2095,
LLVM,NVPTX,2096,(}
LLVM,NVPTX,2097,return FtzRequirement;
LLVM,NVPTX,2098,
LLVM,NVPTX,2099,return {
LLVM,NVPTX,2100,
LLVM,NVPTX,2101,
LLVM,NVPTX,2102,
LLVM,NVPTX,2103,
LLVM,NVPTX,2104,return getGlobalObjectInitType(AS) != GlobalObjectInitType::Undef;
LLVM,NVPTX,2105,
LLVM,NVPTX,2106,return new <ISA_LIT>TargetTransformInfoWrapperPass(TM);
LLVM,NVPTX,2107,
LLVM,NVPTX,2108,
LLVM,NVPTX,2109,AU.setPreservesAll ();
LLVM,NVPTX,2110,
LLVM,NVPTX,2111,"return TargetTransformInfo::getArithmeticInstrCost(Opcode, Ty, Opd1Info, Opd2Info, Opd1PropInfo, Opd2PropInfo);"
LLVM,NVPTX,2112,return hasBranchDivergence;
LLVM,NVPTX,2113,
LLVM,NVPTX,2114,
LLVM,NVPTX,2115,return true;
LLVM,NVPTX,2116,return true;
LLVM,NVPTX,2117,
LLVM,NVPTX,2118,
LLVM,NVPTX,2119,
LLVM,NVPTX,2120,}
LLVM,NVPTX,2121,
LLVM,NVPTX,2122,
LLVM,NVPTX,2123,
LLVM,NVPTX,2124,(getMaximumVectorLoadAlignment(AddrSpace) >= Alignment);
LLVM,NVPTX,2125,
LLVM,NVPTX,2126,return ChainSizeInBytes == 0 && Alignment != 0 && AddrSpace != 0;
LLVM,NVPTX,2127,return true ;
LLVM,NVPTX,2128,
LLVM,NVPTX,2129,temp64 . y = <NUM_LIT> ;
LLVM,NVPTX,2130,
LLVM,NVPTX,2131,
LLVM,NVPTX,2132,
LLVM,NVPTX,2133,
LLVM,NVPTX,2134,
LLVM,NVPTX,2135,}
LLVM,NVPTX,2136,"NVVMAnnotation t(findOneNVVMAnnotation(&F, sits->getName(), y));"
LLVM,NVPTX,2137,
LLVM,NVPTX,2138,
LLVM,NVPTX,2139,return true;
LLVM,NVPTX,2140,return false;
LLVM,NVPTX,2141,"return Static::getReqNTIDx(Internal, x ) }"
LLVM,NVPTX,2142,
LLVM,NVPTX,2143,
LLVM,NVPTX,2144,
LLVM,NVPTX,2145,return val[sampler_name].asString();
LLVM,NVPTX,2146,
LLVM,NVPTX,2147,
LLVM,NVPTX,2148,
LLVM,NVPTX,2149,
LLVM,NVPTX,2150,
LLVM,NVPTX,2151,}
LLVM,NVPTX,2152,
LLVM,NVPTX,2153,
LLVM,NVPTX,2154,}
LLVM,NVPTX,2155,
LLVM,NVPTX,2156,return (x == 0);
LLVM,NVPTX,2157,
LLVM,NVPTX,2158,
LLVM,NVPTX,2159,
LLVM,NVPTX,2160,
LLVM,NVPTX,2161,else {
LLVM,NVPTX,2162,
LLVM,NVPTX,2163,elem->getOperand(1);
LLVM,NVPTX,2164,return tmp;
LLVM,NVPTX,2165,{
LLVM,NVPTX,2166,
LLVM,NVPTX,2167,"cacheAnnotationFromMD ( m , gv ) ;"
LLVM,NVPTX,2168,
LLVM,NVPTX,2169,
LLVM,NVPTX,2170,}
LLVM,NVPTX,2171,"a return statement that returns the value of (bool llvm::findOneNVVMAnnotation(&F, llvm::PropertyAnnotationNames[llvm::PROPERTY_MAXNTID_X], x))."
LLVM,NVPTX,2172,
LLVM,NVPTX,2173,"return the value of the bool expression, which is determined by the result of the llvm::findOneNVVMAnnotation function."
LLVM,NVPTX,2174,
LLVM,NVPTX,2175,
LLVM,NVPTX,2176,
LLVM,NVPTX,2177,None;
LLVM,NVPTX,2178,
LLVM,NVPTX,2179,
LLVM,NVPTX,2180,
LLVM,NVPTX,2181,
LLVM,NVPTX,2182,
LLVM,NVPTX,2183,
LLVM,NVPTX,2184,
LLVM,NVPTX,2185,return false;
LLVM,NVPTX,2186,
LLVM,NVPTX,2187,}
LLVM,NVPTX,2188,}
LLVM,NVPTX,2189,
LLVM,NVPTX,2190,
LLVM,NVPTX,2191,
LLVM,NVPTX,2192,if ( ( * annotationCache ) . find ( m ) != ( * annotationCache ) . end ( ) ) tmp1 [ gv ] = std :: move ( tmp ) ;
LLVM,NVPTX,2193,
LLVM,NVPTX,2194,
LLVM,NVPTX,2195,}
LLVM,NVPTX,2196,
LLVM,NVPTX,2197,
LLVM,NVPTX,2198,
LLVM,NVPTX,2199,}
LLVM,NVPTX,2200,"tmp1 . insert ( std :: pair < const GlobalValue * , Annotation * > ( gv , tmp ) ) ;"
LLVM,NVPTX,2201,}
LLVM,NVPTX,2202,
LLVM,NVPTX,2203,
LLVM,NVPTX,2204,}
LLVM,NVPTX,2205,}
LLVM,NVPTX,2206,}
LLVM,NVPTX,2207,}
LLVM,NVPTX,2208,
LLVM,NVPTX,2209,"Else cacheAnnotationFromMD ( m , gv ) ;"
LLVM,NVPTX,2210,
LLVM,NVPTX,2211,return false;
LLVM,NVPTX,2212,annot.clear();
LLVM,NVPTX,2213,if (!func) {
LLVM,NVPTX,2214,}
LLVM,NVPTX,2215,tmp1 [ gv ] = std ::move( tmp ) if ( ( * annotationCache ) . find ( m ) != ( * annotationCache ) . end ( ) ) {
LLVM,NVPTX,2216,Any data }
LLVM,NVPTX,2217,align = v ;
LLVM,NVPTX,2218,if ( i < <NUM_LIT> && md -> getOperand ( i ) != <PTR_LIT> ) {
LLVM,NVPTX,2219,assert ( Val && <STR_LIT> ) ;
LLVM,NVPTX,2220,
LLVM,NVPTX,2221,if(common == <NUM_LIT>) return PN;
LLVM,NVPTX,2222,( * annotationCache ) [ m ] = std :: move ( tmp1 ) ;
LLVM,NVPTX,2223,
LLVM,NVPTX,2224,
LLVM,NVPTX,2225,print(I->getName());
LLVM,NVPTX,2226,if (I != nullptr) {
LLVM,NVPTX,2227,}
LLVM,NVPTX,2228,
LLVM,NVPTX,2229,}
LLVM,NVPTX,2230,
LLVM,NVPTX,2231,
LLVM,NVPTX,2232,}
LLVM,NVPTX,2233,}
LLVM,NVPTX,2234,
LLVM,NVPTX,2235,x++;
LLVM,NVPTX,2236,"return ( llvm :: findOneNVVMAnnotation ( & F , llvm :: PropertyAnnotationNames [ llvm :: PROPERTY_MAXNTID_Z ] , z ) ) ;"
LLVM,NVPTX,2237,return true;
LLVM,NVPTX,2238,if (F.hasFnAttribute(maxNTIDz)) {
LLVM,NVPTX,2239,
LLVM,NVPTX,2240,"return ( llvm:: findOneNVVMAnnotation( &F, llvm:: PropertyAnnotationNames[llvm::PROPERTY_MAXSM], x ) );"
LLVM,NVPTX,2241,
LLVM,NVPTX,2242,
LLVM,NVPTX,2243,
LLVM,NVPTX,2244,return false;
LLVM,NVPTX,2245,
LLVM,NVPTX,2246,
LLVM,NVPTX,2247,return val.getName();
LLVM,NVPTX,2248,
LLVM,NVPTX,2249,}
LLVM,NVPTX,2250,for (auto it = annot.begin();
LLVM,NVPTX,2251,
LLVM,NVPTX,2252,
LLVM,NVPTX,2253,}
LLVM,NVPTX,2254,
LLVM,NVPTX,2255,
LLVM,NVPTX,2256,
LLVM,NVPTX,2257,Result.clear();
LLVM,NVPTX,2258,break;
LLVM,NVPTX,2259,
LLVM,NVPTX,2260,return true;
LLVM,NVPTX,2261,
LLVM,NVPTX,2262,Pass *RegisterNVVMIntrRangePass = PassRegistry::getPassRegistry()->getPassInstance(nvvm-intr-range);
LLVM,NVPTX,2263,
LLVM,NVPTX,2264,
LLVM,NVPTX,2265,"returned based on the result of runNVVMIntrRange(F, SmVersion)."
LLVM,NVPTX,2266,
LLVM,NVPTX,2267,return Changed;
LLVM,NVPTX,2268,return false;
LLVM,NVPTX,2269,return true;
LLVM,NVPTX,2270,Return Type::getInt64Ty(Context)
LLVM,NVPTX,2271,"case <STR_LIT> : case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , MaxGridSize . y , Call ) ;"
LLVM,NVPTX,2272,"case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , MaxGridSize . y + <NUM_LIT> , Call ) ;"
LLVM,NVPTX,2273,
LLVM,NVPTX,2274,initializeLatencyReducerPass(*PassRegistry::getPassRegistry());
LLVM,NVPTX,2275,
LLVM,NVPTX,2276,
LLVM,NVPTX,2277,:: FunctionPass ( ->ID ) }
LLVM,NVPTX,2278,}
LLVM,NVPTX,2279,
LLVM,NVPTX,2280,
LLVM,NVPTX,2281,
LLVM,NVPTX,2282,
LLVM,NVPTX,2283,
LLVM,NVPTX,2284,initializeNVVMReflectPass(*PassRegistry::getAnalysisUsage());
LLVM,NVPTX,2285,
LLVM,NVPTX,2286,
LLVM,NVPTX,2287,return true ;
LLVM,NVPTX,2288,VarMap[ReflectArg] = ReflectVal;
LLVM,NVPTX,2289,DEBUG(dbgs() << Reflect value:  << ReflectArg << \n);
LLVM,NVPTX,2290,"StringRef ReflectArg = ReflectArg . substr ( <NUM_LIT> , ReflectArg . size ( ) - <NUM_LIT> ) ;"
LLVM,NVPTX,2291,ToRemove.push_back(Call);
LLVM,NVPTX,2292,"Call -> replaceAllUsesWith ( ConstantInt :: get ( Call -> getType ( ) , ReflectVal ) ) ;"
LLVM,NVPTX,2293,
LLVM,NVPTX,2294,
LLVM,NVPTX,2295,
LLVM,NVPTX,2296,:
LLVM,NVPTX,2297,
LLVM,NVPTX,2298,assert (GV->hasName() && Global variables must have names);
LLVM,NVPTX,2299,VarMap[NameValPair[<NUM_LIT>]] = Val;
LLVM,NVPTX,2300,
LLVM,NVPTX,2301,)
LLVM,NVPTX,2302,ToRemove.erase(Call) ;
LLVM,NVPTX,2303,
LLVM,NVPTX,2304,
LLVM,NVPTX,2305,return true;
LLVM,NVPTX,2306,
LLVM,NVPTX,2307,I != E ;
LLVM,NVPTX,2308,
LLVM,NVPTX,2309,Res |= handleFunction(ReflectFunction);
LLVM,NVPTX,2310,
LLVM,NVPTX,2311,
LLVM,NVPTX,2312,allOperands.push_back(oper);
LLVM,NVPTX,2313,}
LLVM,NVPTX,2314,copy->setDesc(InstrInfo->get(getScalarVersion(copy)));
LLVM,NVPTX,2315,"otherOperands.push_back(MachineOperand(MF->getRegInfo(), dest));"
LLVM,NVPTX,2316,
LLVM,NVPTX,2317,
LLVM,NVPTX,2318,return copies[numcopies];
LLVM,NVPTX,2319,
LLVM,NVPTX,2320,
LLVM,NVPTX,2321,
LLVM,NVPTX,2322,
LLVM,NVPTX,2323,
LLVM,NVPTX,2324,dest.setIsDef();
LLVM,NVPTX,2325,copy->addOperand(otherOperands[i]);
LLVM,NVPTX,2326,
LLVM,NVPTX,2327,
LLVM,NVPTX,2328,
LLVM,NVPTX,2329,copies.push_back(copy).
LLVM,NVPTX,2330,"copy->addOperand(MachineOperand::CreateReg(scalarRegs[<NUM_LIT>], false));"
LLVM,NVPTX,2331,copy -> setIsKill ( <NUM_LIT> ) ;
LLVM,NVPTX,2332,
LLVM,NVPTX,2333,copies.push_back(copy);
LLVM,NVPTX,2334,
LLVM,NVPTX,2335,if (which.getImm() < numcopies) {
LLVM,NVPTX,2336,}
LLVM,NVPTX,2337,tm.initialize();
LLVM,NVPTX,2338,
LLVM,NVPTX,2339,
LLVM,NVPTX,2340,
LLVM,NVPTX,2341,
LLVM,NVPTX,2342,
LLVM,NVPTX,2343,return dest.isUndef() ;
LLVM,NVPTX,2344,
LLVM,NVPTX,2345,return RC->isVector();
LLVM,NVPTX,2346,
LLVM,NVPTX,2347,assert (numDefs == <NUM_LIT> );
LLVM,NVPTX,2348,
LLVM,NVPTX,2349,
LLVM,NVPTX,2350,
LLVM,NVPTX,2351,
LLVM,NVPTX,2352,
LLVM,RISCV,0,}
LLVM,RISCV,1,
LLVM,RISCV,2,
LLVM,RISCV,3,
LLVM,RISCV,4,}
LLVM,RISCV,5,}
LLVM,RISCV,6,
LLVM,RISCV,7,
LLVM,RISCV,8,}
LLVM,RISCV,9,
LLVM,RISCV,10,}
LLVM,RISCV,11,}
LLVM,RISCV,12,
LLVM,RISCV,13,return true;
LLVM,RISCV,14,this->STI = STI;
LLVM,RISCV,15,", CommData() {"
LLVM,RISCV,16,
LLVM,RISCV,17,
LLVM,RISCV,18,return _mulh_u8;
LLVM,RISCV,19,unsigned Hi16 = ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ;
LLVM,RISCV,20,
LLVM,RISCV,21,"return (MCFixup::createOffset(Kind, Value, NumBytes);"
LLVM,RISCV,22,"`return create<ISA_LIT>ELFObjectWriter(OS, OSABI, Is64Bit);"
LLVM,RISCV,23,
LLVM,RISCV,24,
LLVM,RISCV,25,}
LLVM,RISCV,26,
LLVM,RISCV,27,return Res;
LLVM,RISCV,28,
LLVM,RISCV,29,"defines a new class called AsmBackend that inherits from the MCAsmBackend class and has two member variables: OSABI and Is64Bit. The constructor of the class takes two parameters: OSABI (which is a uint8_t type) and Is64Bit (which is a boolean). The next statement could potentially be a function or variable declaration within the class, or a call to the constructor using specific values for the parameters. It is not possible to predict the exact statement without more context."
LLVM,RISCV,30,
LLVM,RISCV,31,
LLVM,RISCV,32,return Value ;
LLVM,RISCV,33,Data [ Offset ] |= Value ;
LLVM,RISCV,34,{
LLVM,RISCV,35,}
LLVM,RISCV,36,
LLVM,RISCV,37,
LLVM,RISCV,38,return STI .getFeatureBits()[<STR_LIT>] ;
LLVM,RISCV,39,
LLVM,RISCV,40,return true;
LLVM,RISCV,41,
LLVM,RISCV,42,return Infos [ Kind - FirstTargetFixupKind ] ;
LLVM,RISCV,43,followed by more code that utilizes the returned information about a specific fixup kind.
LLVM,RISCV,44,return Bit11 | ( Bit9_8 << <NUM_LIT> ) | ( Bit6 << <NUM_LIT> ) | ( Bit7 << <NUM_LIT> ) | ( Bit5 << <NUM_LIT> ) | ( Bit4 << <NUM_LIT> ) | ( Bit3_1 << <NUM_LIT> ) ;
LLVM,RISCV,45,Data[Offset + NumBytes + <NUM_LIT>] = uint8_t((Value >> (<NUM_LIT> * <NUM_LIT>)) & <NUM_LIT>);
LLVM,RISCV,46,
LLVM,RISCV,47,"return make_unique<ISA>MCAsmBackend(T, STI, MRI, Options);"
LLVM,RISCV,48,
LLVM,RISCV,49,return Offset == <NUM_LIT> ;
LLVM,RISCV,50,}
LLVM,RISCV,51,", {"
LLVM,RISCV,52,}
LLVM,RISCV,53,"AddFixups ( <NUM_LIT> , {"
LLVM,RISCV,54,It is not possible to accurately predict the next statement without seeing the code and understanding the specific context. Some possible statements that could follow this code snippet could include printf(Error: Unknown opcode);
LLVM,RISCV,55,Res.addOperand(Inst.getOperand(<NUM_LIT>));
LLVM,RISCV,56,
LLVM,RISCV,57,
LLVM,RISCV,58,
LLVM,RISCV,59,
LLVM,RISCV,60,
LLVM,RISCV,61,
LLVM,RISCV,62,if ( ! HasStdExtC ) {
LLVM,RISCV,63,unsigned Bit7 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ;
LLVM,RISCV,64,}
LLVM,RISCV,65,
LLVM,RISCV,66,
LLVM,RISCV,67,
LLVM,RISCV,68,"Fixup.applyFixup(FixedValue, NopBytes, STI);"
LLVM,RISCV,69,
LLVM,RISCV,70,
LLVM,RISCV,71,unsigned Bit1_0 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ;
LLVM,RISCV,72,case <STR_LIT> : break;
LLVM,RISCV,73,
LLVM,RISCV,74,Missing: End of switch statement.
LLVM,RISCV,75,Res.addOperand(MCOperand::createReg(IsCapMode ? <STR_LIT> : <STR_LIT>));
LLVM,RISCV,76,
LLVM,RISCV,77,Value = (Value >> JUMP) & MASK;
LLVM,RISCV,78,}
LLVM,RISCV,79,a case <STR_LIT>: with a condition to set the boolean ShouldForce to true.
LLVM,RISCV,80,
LLVM,RISCV,81,
LLVM,RISCV,82,
LLVM,RISCV,83,if (IsResolved) {
LLVM,RISCV,84,"return create<ISA_LIT>MachOObjectWriter(OS, OSABI, Is64Bit);"
LLVM,RISCV,85,
LLVM,RISCV,86,"%d\n, Value);"
LLVM,RISCV,87,Data[Offset + FullSize] |= uint8_t((Value >> (FullSize * <NUM_LIT>)) & <NUM_LIT>);
LLVM,RISCV,88,if (i != FullSize) {
LLVM,RISCV,89,MCTargetOptions Options = T. Options;
LLVM,RISCV,90,"likely check if the variable Kind is less than the variable FirstTargetFixupKind, and if so, it"
LLVM,RISCV,91,
LLVM,RISCV,92,}
LLVM,RISCV,93,uint64_t Bitfield = ( ( UpperImm & <NUM_LIT> ) << <NUM_LIT> ) | ( LowerImm & <NUM_LIT> ) ;
LLVM,RISCV,94,
LLVM,RISCV,95,if (Type == <STR_LIT>) {
LLVM,RISCV,96,
LLVM,RISCV,97,
LLVM,RISCV,98,
LLVM,RISCV,99,
LLVM,RISCV,100,return Offset > <NUM_LIT> || Offset < - <NUM_LIT> ;
LLVM,RISCV,101,
LLVM,RISCV,102,
LLVM,RISCV,103,if ( Nop16Count != <NUM_LIT> ) {
LLVM,RISCV,104,}
LLVM,RISCV,105,}
LLVM,RISCV,106,"NopBytes.resolve(MCSymbolRefExpr :: create ( <STR_LIT> , Ctx ) , Fixup , FixedValue , AAF , AF )"
LLVM,RISCV,107,Asm.getWriter().emitInstruction(Ret);
LLVM,RISCV,108,
LLVM,RISCV,109,ShouldForce = false ;
LLVM,RISCV,110,unsigned DBit = ( Value >> <NUM_LIT> ) & <NUM_LIT> ;
LLVM,RISCV,111,AsmBackend::getFixupKindInfo(Fixup.getKind())
LLVM,RISCV,112,}
LLVM,RISCV,113,unsigned Hi9 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ;
LLVM,RISCV,114,}
LLVM,RISCV,115,
LLVM,RISCV,116,
LLVM,RISCV,117,
LLVM,RISCV,118,return Offset > <NUM_LIT> || Offset < - <NUM_LIT> ;
LLVM,RISCV,119,}
LLVM,RISCV,120,}
LLVM,RISCV,121,
LLVM,RISCV,122,
LLVM,RISCV,123,}
LLVM,RISCV,124,case <STR_LIT> : return adjust
LLVM,RISCV,125,if (Count % (MinNopLen + 1) == 0) return true;
LLVM,RISCV,126,else if ( const MCSymbolRefExpr * SymRef = dyn_cast < MCSymbolRefExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: createExpr ( SymRef ) ) ;
LLVM,RISCV,127,Inst . execute();
LLVM,RISCV,128,Inst . addOperand ( MCOperand ::createImm(0)) }
LLVM,RISCV,129,"addExpr (Inst, getImm());"
LLVM,RISCV,130,
LLVM,RISCV,131,
LLVM,RISCV,132,return std :: move ( std :: move ( Op ) ) }
LLVM,RISCV,133,Op->Mem.Disp = Disp;
LLVM,RISCV,134,
LLVM,RISCV,135,return Op ;
LLVM,RISCV,136,
LLVM,RISCV,137,}
LLVM,RISCV,138,return Reg;
LLVM,RISCV,139,
LLVM,RISCV,140,
LLVM,RISCV,141,
LLVM,RISCV,142,return isReg (ECUB34Reg) ;
LLVM,RISCV,143,}
LLVM,RISCV,144,}
LLVM,RISCV,145,
LLVM,RISCV,146,
LLVM,RISCV,147,
LLVM,RISCV,148,
LLVM,RISCV,149,
LLVM,RISCV,150,
LLVM,RISCV,151,return false;
LLVM,RISCV,152,
LLVM,RISCV,153,}
LLVM,RISCV,154,
LLVM,RISCV,155,
LLVM,RISCV,156,
LLVM,RISCV,157,
LLVM,RISCV,158,return false;
LLVM,RISCV,159,
LLVM,RISCV,160,
LLVM,RISCV,161,
LLVM,RISCV,162,return isArray ( <IDENT> ) ;
LLVM,RISCV,163,
LLVM,RISCV,164,return opCode == <S>OpCode</S>.U32Imm;
LLVM,RISCV,165,
LLVM,RISCV,166,return _parType == U4_IMM ;
LLVM,RISCV,167,}
LLVM,RISCV,168,
LLVM,RISCV,169,RegisterMCAsmParser < <ISA_LIT>AsmParser > Y ( TheRISCV64Target ) ;
LLVM,RISCV,170,"return Error(ErrorLoc, Invalid operand.);"
LLVM,RISCV,171,}
LLVM,RISCV,172,}
LLVM,RISCV,173,}
LLVM,RISCV,174,
LLVM,RISCV,175,
LLVM,RISCV,176,"to call the function parseRegister with the parameters Operands, 'f', FP64Regs, and <ISA_LIT>Operand::FP64Reg, and return the result as the OperandMatchResultTy data type."
LLVM,RISCV,177,
LLVM,RISCV,178,}
LLVM,RISCV,179,+ }
LLVM,RISCV,180,
LLVM,RISCV,181,
LLVM,RISCV,182,
LLVM,RISCV,183,
LLVM,RISCV,184,
LLVM,RISCV,185,return StartLoc;
LLVM,RISCV,186,}
LLVM,RISCV,187,return Parser.parseNextInstruction();
LLVM,RISCV,188,MCAsmLexerExtension::Initialize(Parser);
LLVM,RISCV,189,return this.Operand;
LLVM,RISCV,190,}
LLVM,RISCV,191,}
LLVM,RISCV,192,<ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;
LLVM,RISCV,193,{
LLVM,RISCV,194,case 'n' : Imm |= <STR_LIT> ;
LLVM,RISCV,195,
LLVM,RISCV,196,Inst.addOperand(ImmOperand(N));
LLVM,RISCV,197,assert ( N == <NUM_LIT> && <STR_LIT> ) ;
LLVM,RISCV,198,
LLVM,RISCV,199,
LLVM,RISCV,200,not execute the evaluateConstantImm function.
LLVM,RISCV,201,
LLVM,RISCV,202,
LLVM,RISCV,203,
LLVM,RISCV,204,
LLVM,RISCV,205,
LLVM,RISCV,206,
LLVM,RISCV,207,
LLVM,RISCV,208,Op -> length = L ;
LLVM,RISCV,209,return Op;
LLVM,RISCV,210,
LLVM,RISCV,211,
LLVM,RISCV,212,
LLVM,RISCV,213,return Op;
LLVM,RISCV,214,
LLVM,RISCV,215,
LLVM,RISCV,216,
LLVM,RISCV,217,}
LLVM,RISCV,218,
LLVM,RISCV,219,
LLVM,RISCV,220,
LLVM,RISCV,221,
LLVM,RISCV,222,"emitJalrInst ( DestReg , DestReg , Symbol , <ISA_LIT>MCExpr::VK_<ISA_LIT>_TLS_LDM , <STR_LIT> , IDLoc , Out ) ;"
LLVM,RISCV,223,
LLVM,RISCV,224,}
LLVM,RISCV,225,
LLVM,RISCV,226,
LLVM,RISCV,227,
LLVM,RISCV,228,if (auto CE = dyn_cast <MCConstantExpr>(Expr)) {
LLVM,RISCV,229,
LLVM,RISCV,230,}
LLVM,RISCV,231,return EndLoc ;
LLVM,RISCV,232,
LLVM,RISCV,233,
LLVM,RISCV,234,return Imm.Val;
LLVM,RISCV,235,return loc + offset;
LLVM,RISCV,236,
LLVM,RISCV,237,
LLVM,RISCV,238,
LLVM,RISCV,239,
LLVM,RISCV,240,return startLoc;
LLVM,RISCV,241,}
LLVM,RISCV,242,throw std::runtime_error(Invalid system register);
LLVM,RISCV,243,}
LLVM,RISCV,244,;
LLVM,RISCV,245,
LLVM,RISCV,246,assert ( ! Val.Type {
LLVM,RISCV,247,if (IsConstantImm) {
LLVM,RISCV,248,"IsValid = <ISA_LIT>AsmParser::classifySymbolRef(getImm(), VK)"
LLVM,RISCV,249,
LLVM,RISCV,250,return Imm && VK;
LLVM,RISCV,251,
LLVM,RISCV,252,<ISA_LIT>MCExpr::VK_<ISA_LIT>_<ISA_LIT>_Error;
LLVM,RISCV,253,IsConstantImm && ( Imm != <NUM_LIT>) && ( isUInt < <NUM_LIT> > ( Imm ) || ( Imm >= <NUM_LIT> && Imm <= <NUM_LIT> ) ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None;
LLVM,RISCV,254,
LLVM,RISCV,255,bool isCSRSystemRegister ( ) const {
LLVM,RISCV,256,after the second return false;
LLVM,RISCV,257,}
LLVM,RISCV,258,return Str.size();
LLVM,RISCV,259,if (SVal) {
LLVM,RISCV,260,
LLVM,RISCV,261,
LLVM,RISCV,262,
LLVM,RISCV,263,}
LLVM,RISCV,264,
LLVM,RISCV,265,
LLVM,RISCV,266,Imm = <ISA_LIT> getImm ( ) ;
LLVM,RISCV,267,return false;
LLVM,RISCV,268,return false;
LLVM,RISCV,269,}
LLVM,RISCV,270,
LLVM,RISCV,271,return true ;
LLVM,RISCV,272,return isImm ( Imm ) && isX86ModRMFilter ( Imm ) ;
LLVM,RISCV,273,return false;
LLVM,RISCV,274,
LLVM,RISCV,275,
LLVM,RISCV,276,"return a boolean value of true if the evaluated constant immediate is not equal to <NUM_LIT>, and if it is a shifted integer with a value less than <NUM_LIT> shifted by <NUM_LIT>. It"
LLVM,RISCV,277,if (!IsConstantImm) return false;
LLVM,RISCV,278,if (IsValid && IsConstantImm) {
LLVM,RISCV,279,}
LLVM,RISCV,280,
LLVM,RISCV,281,
LLVM,RISCV,282,return (0 <= getImm() && getImm() <= 31);
LLVM,RISCV,283,if(IsConstantImm) {
LLVM,RISCV,284,else return getImm ( ) + 1 ;
LLVM,RISCV,285,<ISA_LIT>MCExpr *New = new <ISA_LIT>MCExpr ( VK ) ;
LLVM,RISCV,286,
LLVM,RISCV,287,
LLVM,RISCV,288,}
LLVM,RISCV,289,return (RPARENS (isSR );
LLVM,RISCV,290,
LLVM,RISCV,291,
LLVM,RISCV,292,return false;
LLVM,RISCV,293,
LLVM,RISCV,294,
LLVM,RISCV,295,return IsConstantImm;
LLVM,RISCV,296,
LLVM,RISCV,297,return isInt<32>(Imm) && (VK == MCExpr::VK_Mips_TLS_GD_GPREL || VK == MCExpr::VK_Mips_TLS_LDM || VK == MCExpr::VK_Mips_TLS_GOT_OFF_64 || VK == MCExpr::VK_Mips_GOTTPREL || VK == MCExpr::VK_Mips_TLS_DTPREL_HI || VK == MCExpr::VK_Mips_TLS_LO));
LLVM,RISCV,298,}
LLVM,RISCV,299,if ( IsConstantImm ) return true ;
LLVM,RISCV,300,int64_t Size ;
LLVM,RISCV,301,
LLVM,RISCV,302,if (IsConstantImm) {
LLVM,RISCV,303,
LLVM,RISCV,304,if ( isUImm8Lsb00 ) {
LLVM,RISCV,305,MCExpr::VK_<ISA_LIT>_None
LLVM,RISCV,306,<ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_Hex;
LLVM,RISCV,307,
LLVM,RISCV,308,likely return a boolean value based on the conditions set in the code. It could be something like return true;
LLVM,RISCV,309,
LLVM,RISCV,310,return ( isRV64 ( ) && isUInt < <NUM_LIT> > ( Imm ) ) || isUInt < <NUM_LIT> > ( Imm ) ;
LLVM,RISCV,311,return true;
LLVM,RISCV,312,
LLVM,RISCV,313,
LLVM,RISCV,314,
LLVM,RISCV,315,
LLVM,RISCV,316,
LLVM,RISCV,317,
LLVM,RISCV,318,
LLVM,RISCV,319,}
LLVM,RISCV,320,
LLVM,RISCV,321,<ISA_LIT>VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_Read | return true;
LLVM,RISCV,322,
LLVM,RISCV,323,
LLVM,RISCV,324,
LLVM,RISCV,325,
LLVM,RISCV,326,
LLVM,RISCV,327,"Error ( S , Msg + <STR_LIT> + Twine ( <NUM_LIT> ) + <STR_LIT> ) ;"
LLVM,RISCV,328,if (IDVal == <STR_LIT>) return parseDirectiveEnd();
LLVM,RISCV,329,}
LLVM,RISCV,330,
LLVM,RISCV,331,}
LLVM,RISCV,332,
LLVM,RISCV,333,
LLVM,RISCV,334,return Operands;
LLVM,RISCV,335,
LLVM,RISCV,336,getLexer().Lex();
LLVM,RISCV,337,getLexer ( ) . isNot(AsmToken::Identifier)
LLVM,RISCV,338,If (getLexer().isNot(AsmToken::EndOfFile)
LLVM,RISCV,339,}
LLVM,RISCV,340,
LLVM,RISCV,341,"Operands.push_back(<ISA_LIT>Operand::createImm(Res, S, E, isRV64()));"
LLVM,RISCV,342,}
LLVM,RISCV,343,}
LLVM,RISCV,344,
LLVM,RISCV,345,
LLVM,RISCV,346,
LLVM,RISCV,347,
LLVM,RISCV,348,default: OS << <STR_LIT>Unknown kind<STR_LIT>;
LLVM,RISCV,349,FeatureBitStack . pop_back ( ) ;
LLVM,RISCV,350,
LLVM,RISCV,351,"TargetParser::setTargetTriple(STI.getTargetTriple(), STI.getFeatureBits(), ABIName);"
LLVM,RISCV,352,
LLVM,RISCV,353,
LLVM,RISCV,354,
LLVM,RISCV,355,
LLVM,RISCV,356,return Match_Success ;
LLVM,RISCV,357,}
LLVM,RISCV,358,throw new Error(Invalid operation);
LLVM,RISCV,359,
LLVM,RISCV,360,
LLVM,RISCV,361,
LLVM,RISCV,362,
LLVM,RISCV,363,does not have a next statement as the code ends after the return true;
LLVM,RISCV,364,
LLVM,RISCV,365,
LLVM,RISCV,366,return Match_Success ;
LLVM,RISCV,367,
LLVM,RISCV,368,if (IsConstant) {
LLVM,RISCV,369,assert ( N == <NUM_LIT> && <STR_LIT> ) ;
LLVM,RISCV,370,}
LLVM,RISCV,371,"emitToStreamer ( Out, MCInstBuilder(ADDI) .addReg(DestReg) .addReg(DestReg) .addImm(Lo12));"
LLVM,RISCV,372,
LLVM,RISCV,373,VK = CE -> getKind ( ) ;
LLVM,RISCV,374,if (Val->evaluateAsConstant(Imm)) {
LLVM,RISCV,375,if (IsValid) {
LLVM,RISCV,376,
LLVM,RISCV,377,return Imm;
LLVM,RISCV,378,if (IsConstantImm) {
LLVM,RISCV,379,return false;
LLVM,RISCV,380,to return the boolean expression: IsValid && (VK == MCExpr::VK_<ISA_LIT>_None || VK == MCExpr::VK_<ISA_LIT>_LO || VK == MCExpr::VK_<ISA_LIT>_PCREL_LO).
LLVM,RISCV,381,IsValid = false;
LLVM,RISCV,382,return a boolean value indicating if the VariantKind is equal to either <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None or <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO.
LLVM,RISCV,383,*IsValid = !IsConstantImm && (Imm != <NUM_LIT>) && isInt <<NUM_LIT>>(Imm);
LLVM,RISCV,384,
LLVM,RISCV,385,return true;
LLVM,RISCV,386,"IsConstantImm is a constant immediate, the value of which is less than <NUM_LIT>, and VK equals EL1MCExpr::VK_EL1_None."
LLVM,RISCV,387,<ISA_IMPLCCC>IsValid =  AsmParser :: IsConstantImm;
LLVM,RISCV,388,return IsValid;
LLVM,RISCV,389,evaluate whether the variable 'Imm' is a constant immediate and returns true if it is. It
LLVM,RISCV,390,return IsConstantImm && isUInt64 (Imm) && VK == MCExpr :: VK_Intel_None;
LLVM,RISCV,391,
LLVM,RISCV,392,
LLVM,RISCV,393,a conditional statement where the value of IsConstantImm is checked in order to determine the next course of action for the program. For example: if (IsConstantImm) {
LLVM,RISCV,394,return IsConstantImm;
LLVM,RISCV,395,
LLVM,RISCV,396,if <ISA_LIT>MCExpr :: VK_<ISA_LIT>_<ISA_LIT> {
LLVM,RISCV,397,"return (IsConstantImm && isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Imm ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None) ? <EXPR_RESULT> : <EXPR_RESULT_SLOW> ;"
LLVM,RISCV,398,return ( isRV64 ( ) && isUInt < <NUM_LIT> > ( Imm ) ) && isUInt < <NUM_LIT> > ( Imm ) ;
LLVM,RISCV,399,return true ;
LLVM,RISCV,400,case AsmToken :: String;
LLVM,RISCV,401,SMLoc Loc = getLexer().getLoc();
LLVM,RISCV,402,
LLVM,RISCV,403,
LLVM,RISCV,404,default: OS << Unknown type ;
LLVM,RISCV,405,
LLVM,RISCV,406,default:
LLVM,RISCV,407,if ( o . Shift > 0 ) {
LLVM,RISCV,408,Name != <STR_LIT>;
LLVM,RISCV,409,}
LLVM,RISCV,410,
LLVM,RISCV,411,
LLVM,RISCV,412,"emitToStreamer ( Out , MCInstBuilder ( <STR_LIT> ) . addOperand ( TmpReg ) . addExpr ( RefToLinkTmpLabel ) ) ;"
LLVM,RISCV,413,"emitToStreamer ( Out , MCInstBuilder ( SecondOpcode ) . addOperand ( DestReg ) . addOperand ( TmpReg ) . addExpr ( SymbolLo ) ) ;"
LLVM,RISCV,414,
LLVM,RISCV,415,= Inst.getOpcode();
LLVM,RISCV,416,}
LLVM,RISCV,417,}
LLVM,RISCV,418,
LLVM,RISCV,419,}
LLVM,RISCV,420,"bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ;"
LLVM,RISCV,421,return <ISA_LIT>AsmParser :: classifySymbolRef ( Imm ) ;
LLVM,RISCV,422,
LLVM,RISCV,423,Int64_t Imm ;
LLVM,RISCV,424,
LLVM,RISCV,425,
LLVM,RISCV,426,return Imm;
LLVM,RISCV,427,"MCExpr *Expr = <ISA_LIT>create<ISA_LIT>CK(VK, Imm) ;"
LLVM,RISCV,428,return true;
LLVM,RISCV,429,if (VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_HI || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_GOT_HI || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GOT_HI || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_HI ) {
LLVM,RISCV,430,
LLVM,RISCV,431,
LLVM,RISCV,432,
LLVM,RISCV,433,return MatchOperand_Success ;
LLVM,RISCV,434,<ISA_LIT>->addExplicitOperand ( <ISA_LIT>Operand :: createErrorOperand ( Expected a register after the '
LLVM,RISCV,435,
LLVM,RISCV,436,
LLVM,RISCV,437,"case <STR_LIT> : emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ;"
LLVM,RISCV,438,}
LLVM,RISCV,439,}
LLVM,RISCV,440,
LLVM,RISCV,441,
LLVM,RISCV,442,return MatchOperand_NoMatch;
LLVM,RISCV,443,bool IsRegFPR128 = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg ) ;
LLVM,RISCV,444,
LLVM,RISCV,445,
LLVM,RISCV,446,
LLVM,RISCV,447,if (Res) {
LLVM,RISCV,448,"return generateImmOutOfRangeError ( Operands , ErrorInfo , <STR_LIT> , ErrorLoc, <STR_LIT> ) ;"
LLVM,RISCV,449,
LLVM,RISCV,450,"check if the VK value is equal to either MCExpr::VK_<_CALL or MCExpr::VK_<_CALL_PLT, and if so, call the classifySymbolRef function with the getImm() and Imm parameters, returning the result."
LLVM,RISCV,451,assert ( IsConstantImm && Expected constant imm ) ;
LLVM,RISCV,452,
LLVM,RISCV,453,return false;
LLVM,RISCV,454,
LLVM,RISCV,455,return IsValid && (VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TPREL_HI);
LLVM,RISCV,456,
LLVM,RISCV,457,
LLVM,RISCV,458,}
LLVM,RISCV,459,
LLVM,RISCV,460,"default: emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ;"
LLVM,RISCV,461,return true;
LLVM,RISCV,462,
LLVM,RISCV,463,
LLVM,RISCV,464,
LLVM,RISCV,465,else {
LLVM,RISCV,466,if IsValid == true:
LLVM,RISCV,467,check if VK is equal to <ISA_LIT>MCExpr :: VK_LAV_NONE or <ISA_LIT>MCExpr :: VK_LAV_LO and return the result of that comparison.
LLVM,RISCV,468,assert(Imm == <NUM_LIT> + <NUM_LIT>);
LLVM,RISCV,469,"The value of the variable IsConstantImm is true and the result of the function isShiftedUInt with arguments <NUM_LIT> and <NUM_LIT> is also true for the variable Imm. Additionally, the value of Imm is not equal to <NUM_LIT> and the variable VK is equal to <ISA_LIT>MCExpr::VK_<ISA_LIT>_None."
LLVM,RISCV,470,return IsConstantImm;
LLVM,RISCV,471,
LLVM,RISCV,472,if (IsConstantImm) {
LLVM,RISCV,473,if(IsConstantImm){
LLVM,RISCV,474,MCExpr::isAbsolute() const {
LLVM,RISCV,475,"if (IsConstantImm && isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Imm ) && VK != <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ) {"
LLVM,RISCV,476,return VK == MCExpr::VK_ARM_AMODEIMM && Imm == 0 && IsConstantImm;
LLVM,RISCV,477,"return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ;"
LLVM,RISCV,478,return true ;
LLVM,RISCV,479,getLexer().Lex();
LLVM,RISCV,480,if (parseSymbol(Operands) == MatchOperand_Success) return false;
LLVM,RISCV,481,The predicted statement is return true;
LLVM,RISCV,482,
LLVM,RISCV,483,}
LLVM,RISCV,484,}
LLVM,RISCV,485,
LLVM,RISCV,486,
LLVM,RISCV,487,return false ;
LLVM,RISCV,488,case 'z' : Imm |= abc;
LLVM,RISCV,489,Inst.addOperand(MCOperand::createImm(N));
LLVM,RISCV,490,return Op ;
LLVM,RISCV,491,return Op ;
LLVM,RISCV,492,"emitToStreamer ( Out , MCInstBuilder ( Inst . Opc ) . addReg ( DestReg ) . addReg ( SrcReg ) . addImm ( Inst . Imm ) ) ;"
LLVM,RISCV,493,
LLVM,RISCV,494,
LLVM,RISCV,495,
LLVM,RISCV,496,}
LLVM,RISCV,497,
LLVM,RISCV,498,"return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> <STR_LIT> ) ;"
LLVM,RISCV,499,getParser().Lex();
LLVM,RISCV,500,
LLVM,RISCV,501,
LLVM,RISCV,502,"Error ( getLoc ( ) , Invalidoperand ) ;"
LLVM,RISCV,503,return Res;
LLVM,RISCV,504,
LLVM,RISCV,505,}
LLVM,RISCV,506,return MatchOperand_ParseFail;
LLVM,RISCV,507,
LLVM,RISCV,508,return MatchOperand_Success;
LLVM,RISCV,509,
LLVM,RISCV,510,
LLVM,RISCV,511,
LLVM,RISCV,512,
LLVM,RISCV,513,- Op->EndLoc = E;
LLVM,RISCV,514,Op -> Val = Tok.getNumVal();
LLVM,RISCV,515,return VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None && IsValid
LLVM,RISCV,516,if (IsConstantImm) {
LLVM,RISCV,517,
LLVM,RISCV,518,
LLVM,RISCV,519,
LLVM,RISCV,520,check if VK is equal to <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None.
LLVM,RISCV,521,"IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK , Imm ) ;"
LLVM,RISCV,522,return IsValid;
LLVM,RISCV,523,return IsConstantImm && isUInt <2> (Imm) && VK == MCExpr::VK_VC_None;
LLVM,RISCV,524,if (IsConstantImm) {
LLVM,RISCV,525,
LLVM,RISCV,526,
LLVM,RISCV,527,SMLoc Loc = getLexer().getLoc();
LLVM,RISCV,528,
LLVM,RISCV,529,"Error ( getLoc ( ) , <STR_LIT> ) ;"
LLVM,RISCV,530,
LLVM,RISCV,531,
LLVM,RISCV,532,
LLVM,RISCV,533,return MatchOperand_ParseFail ;
LLVM,RISCV,534,return MatchOperand_NoMatch;
LLVM,RISCV,535,
LLVM,RISCV,536,
LLVM,RISCV,537,}
LLVM,RISCV,538,
LLVM,RISCV,539,
LLVM,RISCV,540,if (IsValid) {
LLVM,RISCV,541,if ( PT.getOpcode() == MCInstrInfo::CALL )
LLVM,RISCV,542,return IsConstantImm && isInt < 64 > ( Imm ) && ( Imm != 0 ) && VK == MCExpr :: VK_Mips_ABS_LO16_None ;
LLVM,RISCV,543,"assigning it to a variable or using it in a conditional statement. For example, if (IsConstantImm) {"
LLVM,RISCV,544,return false;
LLVM,RISCV,545,return false;
LLVM,RISCV,546,}
LLVM,RISCV,547,
LLVM,RISCV,548,}
LLVM,RISCV,549,
LLVM,RISCV,550,
LLVM,RISCV,551,a return statement that checks if the variable VK is equal to either <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None or <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO.
LLVM,RISCV,552,
LLVM,RISCV,553,
LLVM,RISCV,554,
LLVM,RISCV,555,return false ;
LLVM,RISCV,556,if (isRV64()) {
LLVM,RISCV,557,if (SrcReg == <STR_LIT>) {
LLVM,RISCV,558,"emitToStreamer(Out, MCInstBuilder(Inst.Opc).addReg(DestReg).addReg(SrcReg).addImm(Inst.Imm + 1));"
LLVM,RISCV,559,"emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ;"
LLVM,RISCV,560,
LLVM,RISCV,561,Inst.addOperand(MCOperand::createImm(Imm + 1));
LLVM,RISCV,562,
LLVM,RISCV,563,unsigned Opcode = Inst.getOpcode();
LLVM,RISCV,564,
LLVM,RISCV,565,"Inst.addOperand(MCOperand::createReg(VReg,VType.RegisterClass));"
LLVM,RISCV,566,Inst . addOperand ( MCOperand :: createImm ( VType . Data ) ) ;
LLVM,RISCV,567,Op -> VType . Encoding = ( SewLog2 << <NUM_LIT> ) | ( LmulLog2 << <NUM_LIT> ) ;
LLVM,RISCV,568,
LLVM,RISCV,569,return <STR_LIT> ;
LLVM,RISCV,570,return <STR_LIT> ;
LLVM,RISCV,571,
LLVM,RISCV,572,}
LLVM,RISCV,573,case Match_InvalidFRMArg: {
LLVM,RISCV,574,"Error ( getLoc ( ), Expected mask register ) ;"
LLVM,RISCV,575,TailAgnostic = Name.consume_front(<STR_LIT>);
LLVM,RISCV,576,CheckReg = Inst.getOperand(<NUM_LIT>).getReg();
LLVM,RISCV,577,if (Inst.getOperand(<NUM_LIT>).isReg() && CheckReg == DestReg) {
LLVM,RISCV,578,}
LLVM,RISCV,579,
LLVM,RISCV,580,
LLVM,RISCV,581,return false;
LLVM,RISCV,582,return Op;
LLVM,RISCV,583,Out . emitLabel ( TmpLabel ) ;
LLVM,RISCV,584,RefToLinkTmpLabel->print(out.s()) ;
LLVM,RISCV,585,"called with the arguments DestReg, DestReg, Symbol, MCExpr::VK_RISCV_CAPTAB_PCREL_HI, <NUM_LIT>, IDLoc, and Out."
LLVM,RISCV,586,
LLVM,RISCV,587,
LLVM,RISCV,588,"void <ISA_LIT>AsmParser :: emitCapLoadPCRelCap ( MCInst & Inst , SMLoc IDLoc , MCStreamer & Out ) {"
LLVM,RISCV,589,"to call the function emitAuipccInstPair passing in the variables DestReg, DestReg, Symbol, MCExpr::VK_<ISA_LIT>_TLS_GD_CAPTAB_PCREL_HI, <STR_LIT>, IDLoc, and Out."
LLVM,RISCV,590,"added to the output stream, Out."
LLVM,RISCV,591,Out.EmitInstruction(cap_load_tlsie_addr);
LLVM,RISCV,592,}
LLVM,RISCV,593,the opening curly bracket for the function: {
LLVM,RISCV,594,
LLVM,RISCV,595,if ( SymbolId == 0 ) {
LLVM,RISCV,596,
LLVM,RISCV,597,
LLVM,RISCV,598,
LLVM,RISCV,599,}
LLVM,RISCV,600,
LLVM,RISCV,601,return X86II :: getMemoryOperandNo ( Op ) == X86 :: AddrBaseReg && ( L >> 3 ) & 1 ;
LLVM,RISCV,602,
LLVM,RISCV,603,Imm = 10;
LLVM,RISCV,604,return a boolean value stating whether or not IsConstantImm is true.
LLVM,RISCV,605,a conditional statement checking if the VK variable is equal to the <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None value.
LLVM,RISCV,606,VK.setImm(true);
LLVM,RISCV,607,
LLVM,RISCV,608,
LLVM,RISCV,609,e=0;
LLVM,RISCV,610,if (IsConstantImm) {
LLVM,RISCV,611,
LLVM,RISCV,612,"Res = ISA_LITMCExpr :: create ( Res , Kind , getContext ( ) ) ;"
LLVM,RISCV,613,"return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ;"
LLVM,RISCV,614,return false ;
LLVM,RISCV,615,
LLVM,RISCV,616,}
LLVM,RISCV,617,case AsmToken :: IntVal :.
LLVM,RISCV,618,OS << <STR_LIT> << getSpecialCapReg ( ) << '>' ;
LLVM,RISCV,619,case KindTy ::
LLVM,RISCV,620,return false ;
LLVM,RISCV,621,
LLVM,RISCV,622,a return statement that evaluates whether IsValid is true and if VK is equal to <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_HI or <ISA_LIT>MCExpr :: VK_<ISA_LIT>_GOT_HI. It is part of the else condition.
LLVM,RISCV,623,return IsValid && ( VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_HI || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_GOT_HI )
LLVM,RISCV,624,"emitLoadGlobalAddress ( Inst , IDLoc , Out ) ;"
LLVM,RISCV,625,}
LLVM,RISCV,626,}
LLVM,RISCV,627,
LLVM,RISCV,628,return Op;
LLVM,RISCV,629,Op->IsRV128 = IsRV128;
LLVM,RISCV,630,
LLVM,RISCV,631,return <STR_LIT> ;
LLVM,RISCV,632,
LLVM,RISCV,633,
LLVM,RISCV,634,
LLVM,RISCV,635,bool isConstantUImm7 ( ) const;
LLVM,RISCV,636,if (Kind == KindTy :: VectorRegister ) {
LLVM,RISCV,637,return Kind == KindTy :: VType ]
LLVM,RISCV,638,
LLVM,RISCV,639,
LLVM,RISCV,640,if ( HadParens ) getLexer ( ) . UnLex ( LParen ) ;
LLVM,RISCV,641,
LLVM,RISCV,642,if (Name == foo) {
LLVM,RISCV,643,getLexer ( ) . Lex ( ) ;
LLVM,RISCV,644,case KindTy :: Offset : OS << <STR_LIT> << getOffset ( ) << <STR_LIT> ;
LLVM,RISCV,645,break ;
LLVM,RISCV,646,
LLVM,RISCV,647,break ;
LLVM,RISCV,648,
LLVM,RISCV,649,return MatchOperand_Success;
LLVM,RISCV,650,return MatchOperand_ParseFail if the lexer kind is not AsmToken::Identifier.
LLVM,RISCV,651,getLexer().Lex();
LLVM,RISCV,652,"push a new operand (represented by <ISA_LIT>Operand::createToken(<STR_LIT>, FirstS)) onto the Operands vector. If HadParens is false, the code"
LLVM,RISCV,653,"return Error ( ErrorLoc , <STR_LIT> <STR_LIT> ) ;"
LLVM,RISCV,654,None. The code is incomplete and ends with a semicolon (;
LLVM,RISCV,655,The next statement would likely check if the value of VK is equal to ISA_LITMCExpr::VK_<ISA_LIT>_None.
LLVM,RISCV,656,if (IsConstantImm && IsInRange) {
LLVM,RISCV,657,return false;
LLVM,RISCV,658,return RegNo == <NUM_LIT> ;
LLVM,RISCV,659,}
LLVM,RISCV,660,bool IsRegFPR64 = <ISA_LIT>MCRegisterClasses[<STR_LIT>].contains(Reg);
LLVM,RISCV,661,return Match_InvalidOperand;
LLVM,RISCV,662,
LLVM,RISCV,663,if ( getLexer ( ) . getKind ( ) == AsmToken :: ColonColon )
LLVM,RISCV,664,
LLVM,RISCV,665,
LLVM,RISCV,666,if (isIPF()) return true;
LLVM,RISCV,667,
LLVM,RISCV,668,}
LLVM,RISCV,669,"Operands . push_back (<ISA_LIT>Operand :: createImm ( Res , S , E , isRV64 ( ) ) ) ;"
LLVM,RISCV,670,
LLVM,RISCV,671,Op -> VType . PostShuffleInPlace = true;
LLVM,RISCV,672,}
LLVM,RISCV,673,"isConstantImm = evaluateConstantImm(getImm(), Imm, VK);"
LLVM,RISCV,674,if (IsConstantImm) return true;
LLVM,RISCV,675,
LLVM,RISCV,676,
LLVM,RISCV,677,
LLVM,RISCV,678,if (IsValid) {
LLVM,RISCV,679,return ( ( Imm < 64L && Imm >= 0L ) || VK ) ;
LLVM,RISCV,680,if (IsConstantImm) {
LLVM,RISCV,681,if (isImm() && IsConstantImm) IsValid = true;
LLVM,RISCV,682,
LLVM,RISCV,683,}
LLVM,RISCV,684,
LLVM,RISCV,685,
LLVM,RISCV,686,
LLVM,RISCV,687,
LLVM,RISCV,688,if (IsConstantImm) {
LLVM,RISCV,689,}
LLVM,RISCV,690,
LLVM,RISCV,691,return <ISA_LIT>MCExpr::VK_<ISA_LIT>_None_Addr;
LLVM,RISCV,692,if (IsReversible && isInt<NUM_LIT>(Imm) && VK == <ISA_LIT>MCExpr::VK_<ISA_LIT>_None) {
LLVM,RISCV,693,
LLVM,RISCV,694,return ( VK == VK_UImm8 ) ;
LLVM,RISCV,695,Op->setSExtWidth(Sew);
LLVM,RISCV,696,a statement related to a default case or a closing brace for the switch statement. For example: default: return null;
LLVM,RISCV,697,break;
LLVM,RISCV,698,
LLVM,RISCV,699,
LLVM,RISCV,700,return true ;
LLVM,RISCV,701,"if ( DestReg == MaskReg ) return Error ( Loc , <STR_LIT> <STR_LIT> ) ;"
LLVM,RISCV,702,
LLVM,RISCV,703,
LLVM,RISCV,704,
LLVM,RISCV,705,if (IsValid) {
LLVM,RISCV,706,"Error ( getLoc ( ) , <STR_LIT> ) ;"
LLVM,RISCV,707,if ( Result == MatchOperand_Success ) return false;
LLVM,RISCV,708,
LLVM,RISCV,709,case ';
LLVM,RISCV,710,case 's' : Imm |= <STR_LIT> ;
LLVM,RISCV,711,
LLVM,RISCV,712,
LLVM,RISCV,713,Op->Reg.RegNum = RegNo;
LLVM,RISCV,714,
LLVM,RISCV,715,
LLVM,RISCV,716,
LLVM,RISCV,717,
LLVM,RISCV,718,
LLVM,RISCV,719,
LLVM,RISCV,720,
LLVM,RISCV,721,
LLVM,RISCV,722,}
LLVM,RISCV,723,return StringRef();
LLVM,RISCV,724,if (IsValid) NextStatement();
LLVM,RISCV,725,
LLVM,RISCV,726,
LLVM,RISCV,727,
LLVM,RISCV,728,
LLVM,RISCV,729,}
LLVM,RISCV,730,return true;
LLVM,RISCV,731,}
LLVM,RISCV,732,"R -- return IsConstantImm && ( Imm != <<NUM_LIT>> ) && isShiftedInt <<NUM_LIT>> , <<NUM_LIT>> > ( Imm ) && VK == <<ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;"
LLVM,RISCV,733,return false;
LLVM,RISCV,734,
LLVM,RISCV,735,
LLVM,RISCV,736,
LLVM,RISCV,737,
LLVM,RISCV,738,
LLVM,RISCV,739,if ( ! isPtr() ) {
LLVM,RISCV,740,
LLVM,RISCV,741,}
LLVM,RISCV,742,
LLVM,RISCV,743,
LLVM,RISCV,744,"if (IsConstantImm && isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Imm ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None) {"
LLVM,RISCV,745,
LLVM,RISCV,746,
LLVM,RISCV,747,
LLVM,RISCV,748,return ( isRV64 ( ) && isUInt < <NUM_LIT> > ( Imm ) ) || isUInt < <NUM_LIT> > ( Imm ) ;
LLVM,RISCV,749,
LLVM,RISCV,750,return MatchOperand_Success;
LLVM,RISCV,751,
LLVM,RISCV,752,return true;
LLVM,RISCV,753,
LLVM,RISCV,754,"Possible options include: emit warning with parameters (<STR_LIT>, <STR_LIT>), and eat to the end of the statement."
LLVM,RISCV,755,
LLVM,RISCV,756,MAB . setForceRelocs ( ) ;
LLVM,RISCV,757,
LLVM,RISCV,758,return MatchOperand_NoMatch ;
LLVM,RISCV,759,
LLVM,RISCV,760,
LLVM,RISCV,761,
LLVM,RISCV,762,}
LLVM,RISCV,763,"Parser . addAliasForDirective ( <STR_LIT> , <STR_LIT> ) ;"
LLVM,RISCV,764,
LLVM,RISCV,765,default:
LLVM,RISCV,766,else {
LLVM,RISCV,767,Stubs.clear();
LLVM,RISCV,768,most likely closing curly brace }
LLVM,RISCV,769,
LLVM,RISCV,770,
LLVM,RISCV,771,}
LLVM,RISCV,772,A.Run();
LLVM,RISCV,773,
LLVM,RISCV,774,
LLVM,RISCV,775,
LLVM,RISCV,776,
LLVM,RISCV,777,
LLVM,RISCV,778,llvm_unreachable(<STR_LIT>) ;
LLVM,RISCV,779,
LLVM,RISCV,780,
LLVM,RISCV,781,
LLVM,RISCV,782,
LLVM,RISCV,783,if ( Res ) {
LLVM,RISCV,784,
LLVM,RISCV,785,
LLVM,RISCV,786,llvm :: <OS_MATCH_TYPE>raw_ostream & OS = * OutStreamer ;
LLVM,RISCV,787,AsmPrinter :: OutStreamer -> Flush ( ) ;
LLVM,RISCV,788,if ( Res ) {
LLVM,RISCV,789,}
LLVM,RISCV,790,}
LLVM,RISCV,791,if ( MO.getImm() != <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ;
LLVM,RISCV,792,}
LLVM,RISCV,793,OS << MO;
LLVM,RISCV,794,
LLVM,RISCV,795,
LLVM,RISCV,796,RTS.emitDirective(  .text  ) ;
LLVM,RISCV,797,
LLVM,RISCV,798,break ;
LLVM,RISCV,799,
LLVM,RISCV,800,TargetStreamer & MCT = RTS->getTargetStreamer();
LLVM,RISCV,801,
LLVM,RISCV,802,RTS.emitDirectiveOptionPop();
LLVM,RISCV,803,
LLVM,RISCV,804,<ISA_LIT>TargetStreamer & RTS = static_cast < <ISA_LIT>TargetStreamer & > ( * OutStreamer -> getTargetStreamer ( ) ) ;
LLVM,RISCV,805,RTS.emitRVFIHWLPBasicBlock(MBB);
LLVM,RISCV,806,RVFI->analyze();
LLVM,RISCV,807,
LLVM,RISCV,808,
LLVM,RISCV,809,
LLVM,RISCV,810,return true;
LLVM,RISCV,811,
LLVM,RISCV,812,
LLVM,RISCV,813,}
LLVM,RISCV,814,}
LLVM,RISCV,815,RTS.emitAssemblerEnd(M);
LLVM,RISCV,816,
LLVM,RISCV,817,emitFunctionBodyStart();
LLVM,RISCV,818,RTS.setTargetFeatures(STI->getTargetFeatures());
LLVM,RISCV,819,"emitPseudoExpansionLowering(OutStreamer, MI);"
LLVM,RISCV,820,const MachineInstr & const MI = * InstrInfo ;
LLVM,RISCV,821,CInst . setLoc ( Inst . getLoc ( ) ) ;
LLVM,RISCV,822,S.EmitInstruction(Inst);
LLVM,RISCV,823,
LLVM,RISCV,824,}
LLVM,RISCV,825,OS << MO.getGlobal()->getName();
LLVM,RISCV,826,
LLVM,RISCV,827,
LLVM,RISCV,828,
LLVM,RISCV,829,
LLVM,RISCV,830,if ( FeaturesRequired.contains(ActiveFeatures[<STR_LIT>]) ) return true;
LLVM,RISCV,831,
LLVM,RISCV,832,if ( IsRV64 ) return ABI_LP64 .
LLVM,RISCV,833,
LLVM,RISCV,834,return SEW * 8 ;
LLVM,RISCV,835,break;
LLVM,RISCV,836,return VLMULBits * VSEWBits;
LLVM,RISCV,837,return combinedEncoding;
LLVM,RISCV,838,return isCheriPureCapABI ( TargetABI ) ? Target uses the CHERI pure-capability ABI : Target does not use the CHERI pure-capability ABI;
LLVM,RISCV,839,return TSFlags & VConstraintBits;
LLVM,RISCV,840,
LLVM,RISCV,841,
LLVM,RISCV,842,
LLVM,RISCV,843,
LLVM,RISCV,844,
LLVM,RISCV,845,}
LLVM,RISCV,846,
LLVM,RISCV,847,
LLVM,RISCV,848,
LLVM,RISCV,849,OS << <STR_LIT>;
LLVM,RISCV,850,}
LLVM,RISCV,851,
LLVM,RISCV,852,
LLVM,RISCV,853,
LLVM,RISCV,854,return static_cast < int8_t > (SEWIndex) ;
LLVM,RISCV,855,
LLVM,RISCV,856,
LLVM,RISCV,857,
LLVM,RISCV,858,unsigned VLMUL = ( VType & <NUM_LIT> ) | ( ( VType & <NUM_LIT> ) >> <NUM_LIT> ) ;
LLVM,RISCV,859,
LLVM,RISCV,860,unsigned LMUL = ( VType >> 8 ) & 3 ;
LLVM,RISCV,861,
LLVM,RISCV,862,Offset++;
LLVM,RISCV,863,if (hasVecPolicyOp(TSFlags)) {
LLVM,RISCV,864,
LLVM,RISCV,865,return Desc.getNumOperands() - Offset;
LLVM,RISCV,866,}
LLVM,RISCV,867,
LLVM,RISCV,868,
LLVM,RISCV,869,
LLVM,RISCV,870,
LLVM,RISCV,871,
LLVM,RISCV,872,
LLVM,RISCV,873,
LLVM,RISCV,874,return static_cast < <ISA_LIT>VSEW > ( VSEW ) * 2 ;
LLVM,RISCV,875,}
LLVM,RISCV,876,}
LLVM,RISCV,877,
LLVM,RISCV,878,a declaration of a boolean variable named result or output and an initialization of it to equal the value returned by the function writesElement0. For example: bool result = writesElement0();
LLVM,RISCV,879,return FeatureVector;
LLVM,RISCV,880,: FeatureVector.push_back(std::string() + Feature.Key);
LLVM,RISCV,881,
LLVM,RISCV,882,if (TailAgnostic) {
LLVM,RISCV,883,
LLVM,RISCV,884,
LLVM,RISCV,885,
LLVM,RISCV,886,}
LLVM,RISCV,887,OS << <STR_LIT> ;
LLVM,RISCV,888,
LLVM,RISCV,889,errs ( ) << <STR_LIT> <STR_LIT> ;
LLVM,RISCV,890,getVSEW = 1 ;
LLVM,RISCV,891,
LLVM,RISCV,892,
LLVM,RISCV,893,return this.bpRegister;
LLVM,RISCV,894,
LLVM,RISCV,895,
LLVM,RISCV,896,
LLVM,RISCV,897,
LLVM,RISCV,898,
LLVM,RISCV,899,if (VType == 1) {
LLVM,RISCV,900,
LLVM,RISCV,901,return TSFlags & HasDummyMaskOpMask;
LLVM,RISCV,902,}
LLVM,RISCV,903,
LLVM,RISCV,904,{
LLVM,RISCV,905,}
LLVM,RISCV,906,
LLVM,RISCV,907,
LLVM,RISCV,908,
LLVM,RISCV,909,cout << The value is returned.;
LLVM,RISCV,910,return float ;
LLVM,RISCV,911,
LLVM,RISCV,912,}
LLVM,RISCV,913,default : llvm_unreachable ( <STR_LIT> ) ;
LLVM,RISCV,914,
LLVM,RISCV,915,if (Str.equals(UP)) {
LLVM,RISCV,916,
LLVM,RISCV,917,
LLVM,RISCV,918,
LLVM,RISCV,919,MBBStartOffset += <NUM_LIT>;
LLVM,RISCV,920,
LLVM,RISCV,921,}
LLVM,RISCV,922,}
LLVM,RISCV,923,}
LLVM,RISCV,924,
LLVM,RISCV,925,EverMadeChange |= MadeChange ;
LLVM,RISCV,926,
LLVM,RISCV,927,
LLVM,RISCV,928,
LLVM,RISCV,929,
LLVM,RISCV,930,<<TARGET_SET ( __cdecl <<FUNCTION_CODE ( __thiscall <<CLASS_CODE ( TLI ) ) ) return new <<CLASS_CODE ( TLI ) ;
LLVM,RISCV,931,register = MI. getOperand ( <NUM_LIT> ).getReg();
LLVM,RISCV,932,}
LLVM,RISCV,933,
LLVM,RISCV,934,
LLVM,RISCV,935,}
LLVM,RISCV,936,}
LLVM,RISCV,937,}
LLVM,RISCV,938,return MachineFunctionProperties().set(MachineFunctionProperties::Property::IsSSA).set(MachineFunctionProperties::Property::IsAlignmentCorrected);
LLVM,RISCV,939,return false;
LLVM,RISCV,940,
LLVM,RISCV,941,Pass * CleanupVSETVLIPass = PassRegistry::getPassRegistry()->getPass(ISA_LIT);
LLVM,RISCV,942,
LLVM,RISCV,943,if ( ST.getFeatureBits() & RISCV::FeatureStdExtV) return false;
LLVM,RISCV,944,
LLVM,RISCV,945,if (IsRV64) {
LLVM,RISCV,946,
LLVM,RISCV,947,}
LLVM,RISCV,948,return Align (Size);
LLVM,RISCV,949,
LLVM,RISCV,950,ID . SubtractDecimal ( 8 ) ;
LLVM,RISCV,951,}
LLVM,RISCV,952,
LLVM,RISCV,953,It is not possible to predict the next statement without more context about the code. could be any valid code following the  return GV;
LLVM,RISCV,954,}
LLVM,RISCV,955,
LLVM,RISCV,956,
LLVM,RISCV,957,return Modifier;
LLVM,RISCV,958,<ISA_LIT>IntegerConversion :: <QUOTE>IntegerConversion <$/QUOTE>
LLVM,RISCV,959,
LLVM,RISCV,960,
LLVM,RISCV,961,
LLVM,RISCV,962,
LLVM,RISCV,963,}
LLVM,RISCV,964,
LLVM,RISCV,965,
LLVM,RISCV,966,return MCDisassembler_Fail;
LLVM,RISCV,967,
LLVM,RISCV,968,Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ;
LLVM,RISCV,969,
LLVM,RISCV,970,return MCDisassembler :: Success;
LLVM,RISCV,971,return ERROR;
LLVM,RISCV,972,Compile error: <STR_LIT> cannot be concatenated with RegNo.
LLVM,RISCV,973,return Inst;
LLVM,RISCV,974,
LLVM,RISCV,975,Inst.addOperand(MCOperand::createReg(Reg)).
LLVM,RISCV,976,Inst.addOperand(Inst.getOperand(<NUM_LIT>));
LLVM,RISCV,977,"DecodeGPRRegisterClass(Inst, Rs2, Address, Decoder);"
LLVM,RISCV,978,
LLVM,RISCV,979,"DecodeGPRRegisterClass ( Inst , Rs2 , Address , Decoder ) ;"
LLVM,RISCV,980,
LLVM,RISCV,981,assert (Result == MCDisassembler::Success && <STR_LIT>);
LLVM,RISCV,982,return the DecodeStatus variable Result as MCDisassembler::Success.
LLVM,RISCV,983,"Result = decodeSImmOperand < <NUM_LIT> > ( Inst , SImm6 , Address , Decoder ) ;"
LLVM,RISCV,984,
LLVM,RISCV,985,return Reg;
LLVM,RISCV,986,}
LLVM,RISCV,987,}
LLVM,RISCV,988,"TargetRegistry::RegisterMCDisassembler(getThe<ISA_LIT>64Target(), create<ISA_LIT>Disassembler);"
LLVM,RISCV,989,the closing curly brace for the Disassembler constructor: }
LLVM,RISCV,990,return;
LLVM,RISCV,991,
LLVM,RISCV,992,else {
LLVM,RISCV,993,
LLVM,RISCV,994,}
LLVM,RISCV,995,return MCDisassembler :: Success ;
LLVM,RISCV,996,The code is successful if an operand is added and the program returns MCDisassembler :: Success.
LLVM,RISCV,997,if ( RegNo >= <NUM_LIT> ) {
LLVM,RISCV,998,
LLVM,RISCV,999,}
LLVM,RISCV,1000,return DecodeStatus::Fail;
LLVM,RISCV,1001,MCDisassembler :: Fail
LLVM,RISCV,1002,
LLVM,RISCV,1003,return MCDisassembler :: Success ;
LLVM,RISCV,1004,MCDisassembler :: Success
LLVM,RISCV,1005,return MCDisassembler :: Success ;
LLVM,RISCV,1006,if (RegNo >= 32 || (IsRV32E && RegNo >= 32)) return MCDisassembler::Fail;
LLVM,RISCV,1007,return Reg;
LLVM,RISCV,1008,Inst.addOperand(MCOperand::createImm(Address));
LLVM,RISCV,1009,RI->getNumRegs();
LLVM,RISCV,1010,return MCDisassembler::Success;
LLVM,RISCV,1011,Inst.addOperand(MCOperand :: createReg(Reg));
LLVM,RISCV,1012,
LLVM,RISCV,1013,"a return statement, potentially returning a MCDisassembler::Fail value."
LLVM,RISCV,1014,return Reg;
LLVM,RISCV,1015,Size = <NUM_LIT> ;
LLVM,RISCV,1016,Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT + RegNo> ) ) ;
LLVM,RISCV,1017,return MCDisassembler::SuccessWithInfo;
LLVM,RISCV,1018,"If the RegNo is greater than or equal to NUM_LIT, return MCDisassembler::Fail. Then, create a new register using the string literal and the RegNo, and add it as an operand to the instruction."
LLVM,RISCV,1019,return MCDisassembler::Success;
LLVM,RISCV,1020,Inst.encode();
LLVM,RISCV,1021,
LLVM,RISCV,1022,return MCDisassembler::Success;
LLVM,RISCV,1023,Inst.setOpcode(ADD);
LLVM,RISCV,1024,return MCDisassembler :: Success ;
LLVM,RISCV,1025,
LLVM,RISCV,1026,
LLVM,RISCV,1027,Inst . addOperand ( MCOperand :: createImm ( Imm ) ) ;
LLVM,RISCV,1028,
LLVM,RISCV,1029,Inst.addOperand(MCOperand::createReg(Reg));
LLVM,RISCV,1030,
LLVM,RISCV,1031,}
LLVM,RISCV,1032,
LLVM,RISCV,1033,return MCDisassembler::Fail;
LLVM,RISCV,1034,returns MCDisassembler::Success.
LLVM,RISCV,1035,}
LLVM,RISCV,1036,MCDisassembler::Fail
LLVM,RISCV,1037,"Result = decodeInstruction (DecoderTable16, MI, Insn, Address, this, STI);"
LLVM,RISCV,1038,"return (getNextInstr(Inst, Address) == 0) ? Success : Fail;"
LLVM,RISCV,1039,
LLVM,RISCV,1040,
LLVM,RISCV,1041,Inst.execute();
LLVM,RISCV,1042,Inst .addOperand( MCOperand::createReg(Reg) );
LLVM,RISCV,1043,return Inst;
LLVM,RISCV,1044,}
LLVM,RISCV,1045,if ( RegNo == 0 ) return MCDisassembler :: Success;
LLVM,RISCV,1046,
LLVM,RISCV,1047,
LLVM,RISCV,1048,return MCDisassembler :: Success ;
LLVM,RISCV,1049,
LLVM,RISCV,1050,
LLVM,RISCV,1051,return MCDisassembler :: Success ;
LLVM,RISCV,1052,
LLVM,RISCV,1053,}
LLVM,RISCV,1054,Reg = RA;
LLVM,RISCV,1055,else if ( RegNo == 0 ) return MCDisassembler ::SoftFail;
LLVM,RISCV,1056,Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ;
LLVM,RISCV,1057,Inst.setOpcode(X86::FPR32RegClass);
LLVM,RISCV,1058,(}
LLVM,RISCV,1059,
LLVM,RISCV,1060,return MCDisassembler :: Success ;
LLVM,RISCV,1061,return MCDisassembler :: Success.
LLVM,RISCV,1062,
LLVM,RISCV,1063,
LLVM,RISCV,1064,
LLVM,RISCV,1065,
LLVM,RISCV,1066,
LLVM,RISCV,1067,return MCDisassembler :: Success }
LLVM,RISCV,1068,}
LLVM,RISCV,1069,return Reg;
LLVM,RISCV,1070,return DecodeStatus::Fail;
LLVM,RISCV,1071,to assert that the Result is equal to the MCDisassembler::Success and that the instruction has successfully been decoded.
LLVM,RISCV,1072,Inst.addOperand(MCOperand::createReg(Rd));
LLVM,RISCV,1073,MCDisassembler::Success
LLVM,RISCV,1074,
LLVM,RISCV,1075,"return decodeSImmOperand <N> (Inst, Imm + 1, Address, Decoder);"
LLVM,RISCV,1076,else if ( Imm == <BIT_LIT> ) return MCDisassembler :: Success ;
LLVM,RISCV,1077,"RegisterOperand decodeOperand ( MCInst & Inst , uint64_t Imm , int64_t Address , const MCDisassembler * Decoder ) {"
LLVM,RISCV,1078,MCInst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm << (NUM_LIT))))
LLVM,RISCV,1079,MCInst.addOperand(MCOperand::createImm(SignExted64 < N > (Imm << <NUM_LIT>))) ;
LLVM,RISCV,1080,"return decodeImmOperand < N+1 > ( Inst , Imm , Address , Decoder ) ;"
LLVM,RISCV,1081,
LLVM,RISCV,1082,}
LLVM,RISCV,1083,Inst.addOperand(MCOperand::createImm(Offset));
LLVM,RISCV,1084,MCDisassembler::Success
LLVM,RISCV,1085,Inst.addOperand(MCOperand::createImm(RegNo));
LLVM,RISCV,1086,
LLVM,RISCV,1087,const MCRegisterClass *RC = <ISA_LIT> :: <REG_CLASS>;
LLVM,RISCV,1088,
LLVM,RISCV,1089,"DecodeGPRRegisterClass ( Inst , <NUM_LIT> , Address , Decoder );"
LLVM,RISCV,1090,
LLVM,RISCV,1091,}
LLVM,RISCV,1092,Inst.addOperand (MCOperand::createImm (Imm)) ;
LLVM,RISCV,1093,MCDisassembler::Success
LLVM,RISCV,1094,return MCDisassembler::Success;
LLVM,RISCV,1095,MCDisassembler :: Success
LLVM,RISCV,1096,return MCDisassembler :: Success ;
LLVM,RISCV,1097,if (Decoder == nullptr) {
LLVM,RISCV,1098,return MCDisassembler::Success;
LLVM,RISCV,1099,Inst.getOperand(0).getReg();
LLVM,RISCV,1100,return DecodeSuccess;
LLVM,RISCV,1101,
LLVM,RISCV,1102,
LLVM,RISCV,1103,
LLVM,RISCV,1104,
LLVM,RISCV,1105,
LLVM,RISCV,1106,
LLVM,RISCV,1107,Inst.execute();
LLVM,RISCV,1108,Inst.addOperand(MCOperand::createReg(Reg));
LLVM,RISCV,1109,DecodeStatus status = MCDisassembler::Fail;
LLVM,RISCV,1110,
LLVM,RISCV,1111,Inst.execute();
LLVM,RISCV,1112,return inst.setOpcode( uint64_t Imm);
LLVM,RISCV,1113,
LLVM,RISCV,1114,
LLVM,RISCV,1115,
LLVM,RISCV,1116,
LLVM,RISCV,1117,return ELF :: R_<ISA_LIT>_CALL_PLT ;
LLVM,RISCV,1118,
LLVM,RISCV,1119,
LLVM,RISCV,1120,
LLVM,RISCV,1121,
LLVM,RISCV,1122,return ELF :: R_<ISA_LIT>_NONE
LLVM,RISCV,1123,return ELF :: R_<ISA_LIT>_TPREL_SUB ;
LLVM,RISCV,1124,
LLVM,RISCV,1125,return ELF :: R_<ISA_LIT>_RELATIVE ;
LLVM,RISCV,1126,return MOTW;
LLVM,RISCV,1127,return ELF::R_X86_64_64;
LLVM,RISCV,1128,
LLVM,RISCV,1129,
LLVM,RISCV,1130,return ELF :: R_<ISA_LIT>_PCREL_LO12_S ;
LLVM,RISCV,1131,label <STR_LIT>:
LLVM,RISCV,1132,return ELF :: R_<ISA_LIT>_ADD16S ;
LLVM,RISCV,1133,
LLVM,RISCV,1134,"Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ;"
LLVM,RISCV,1135,return ELF :: R_<ISA_LIT>_NONE ;
LLVM,RISCV,1136,if ( Expr -> getKind ( ) == MCExpr :: Target && cast < <ISA_LIT>MCExpr > ( Expr ) -> getKind ( ) == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_32_PCREL ) return ELF :: R_<ISA_LIT>_32_PCREL ;
LLVM,RISCV,1137,case <STR_LIT> : return ELF :: R_<ISA_LIT>_JALR ;
LLVM,RISCV,1138,return ELF :: R_<ISA_LIT>_CALL26 ;
LLVM,RISCV,1139,
LLVM,RISCV,1140,possibly create a unique <code>{
LLVM,RISCV,1141,"case FK_Cti : Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ;"
LLVM,RISCV,1142,case AttributeType :: Block : Result += getULEB128Size ( item . Tag ) ;
LLVM,RISCV,1143,}
LLVM,RISCV,1144,
LLVM,RISCV,1145,
LLVM,RISCV,1146,
LLVM,RISCV,1147,
LLVM,RISCV,1148,
LLVM,RISCV,1149,
LLVM,RISCV,1150,
LLVM,RISCV,1151,return;
LLVM,RISCV,1152,
LLVM,RISCV,1153,}
LLVM,RISCV,1154,return;
LLVM,RISCV,1155,a curly brace {
LLVM,RISCV,1156,assert (!OptionsStack.empty() && Cannot push an empty options stack);
LLVM,RISCV,1157,
LLVM,RISCV,1158,
LLVM,RISCV,1159,
LLVM,RISCV,1160,return;
LLVM,RISCV,1161,
LLVM,RISCV,1162,
LLVM,RISCV,1163,break ;
LLVM,RISCV,1164,
LLVM,RISCV,1165,Streamer . emitInt32 ( 0 ) ;
LLVM,RISCV,1166,"return std :: make_pair ( <STR_LIT> , <STR_LIT> ) ;"
LLVM,RISCV,1167,"return std :: make_pair ( <STR_LIT> , <STR_LIT> );"
LLVM,RISCV,1168,return MBE -> isRelocatable ( ) ;
LLVM,RISCV,1169,return false;
LLVM,RISCV,1170,uint64_t <ISA_LIT> Offset = 0;
LLVM,RISCV,1171,
LLVM,RISCV,1172,
LLVM,RISCV,1173,
LLVM,RISCV,1174,
LLVM,RISCV,1175,
LLVM,RISCV,1176,ELF   ELF :: EF_<ISA_LIT>_RVC
LLVM,RISCV,1177,if (EFlags |= ELF :: EF_<ISA_LIT>_LP64) {
LLVM,RISCV,1178,
LLVM,RISCV,1179,
LLVM,RISCV,1180,
LLVM,RISCV,1181,
LLVM,RISCV,1182,
LLVM,RISCV,1183,}
LLVM,RISCV,1184,
LLVM,RISCV,1185,
LLVM,RISCV,1186,}
LLVM,RISCV,1187,}
LLVM,RISCV,1188,
LLVM,RISCV,1189,"BuildMI (LoopMBB, DL, TII->get(<STR_LIT>), ScratchReg).addReg(DestReg).addReg(IncrReg);"
LLVM,RISCV,1190,break ;
LLVM,RISCV,1191,
LLVM,RISCV,1192,
LLVM,RISCV,1193,"BuildMI(DoneMBB, DL, TII->get(<STR_LIT>), DoneMBB);"
LLVM,RISCV,1194,
LLVM,RISCV,1195,throw new std ::runtime_error ( Unknown RMW width ) }
LLVM,RISCV,1196,`return <STR_LIT> ;
LLVM,RISCV,1197,return PtrIsCap ? <STR_LIT> : <STR_LIT> ;
LLVM,RISCV,1198,
LLVM,RISCV,1199,return PtrIsCap ? <STR_LIT> : <STR_LIT> ;
LLVM,RISCV,1200,return PtrIsCap ? <STR_LIT> :
LLVM,RISCV,1201,}
LLVM,RISCV,1202,
LLVM,RISCV,1203,"if ( Width == <NUM_LIT> ) return getSCForRMW64 ( PtrIsCap , Ordering ) ;"
LLVM,RISCV,1204,
LLVM,RISCV,1205,return PtrIsCap ? <STR_LIT> : <STR_LIT> ;
LLVM,RISCV,1206,return PtrIsCap ? <STR_LIT> : <STR_LIT> ;
LLVM,RISCV,1207,
LLVM,RISCV,1208,? <STR_LIT> : <STR_LIT> ) : ( PtrIsCap ? <STR_LIT> : <STR_LIT> ) ;
LLVM,RISCV,1209,"BuildMI (LoopMBB, DL, TII -> get (AddOp), DestReg).addReg(ResultReg).addReg(OperandReg);"
LLVM,RISCV,1210,
LLVM,RISCV,1211,"BuildMI ( LoopMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( ScratchReg ) . addReg ( <STR_LIT> ) . addMBB ( LoopMBB ) ;"
LLVM,RISCV,1212,
LLVM,RISCV,1213,
LLVM,RISCV,1214,{
LLVM,RISCV,1215,break ;
LLVM,RISCV,1216,}
LLVM,RISCV,1217,"case <STR_LIT> : return expandAtomicLoadAdd ( MBB , MBBI , AtomicRMWInst :: Or , true , <NUM_LIT> , NextMBBI )"
LLVM,RISCV,1218,"return expandAtomicCmpXchg ( MBB, MBBI, false, <NUM_LIT>, NextMBBI);"
LLVM,RISCV,1219,if ( Width == <NUM_LIT> ) return getLRForSC64 (Ordering);
LLVM,RISCV,1220,return <STR_LIT> ;
LLVM,RISCV,1221,
LLVM,RISCV,1222,case AtomicOrdering :: SequentiallyConsistent : return <STR_LIT> ;
LLVM,RISCV,1223,return EntryPointSplittingPass;
LLVM,RISCV,1224,if (Ordering == AtomicOrdering::Monotonic) {
LLVM,RISCV,1225,return <STR_LIT> ;
LLVM,RISCV,1226,
LLVM,RISCV,1227,return <STR_LIT> ;
LLVM,RISCV,1228,
LLVM,RISCV,1229,
LLVM,RISCV,1230,
LLVM,RISCV,1231,
LLVM,RISCV,1232,
LLVM,RISCV,1233,
LLVM,RISCV,1234,
LLVM,RISCV,1235,}
LLVM,RISCV,1236,LLVM_DEBUG(dbgs() << Running ExpandCoreVHwlpPseudo\n);
LLVM,RISCV,1237,
LLVM,RISCV,1238,
LLVM,RISCV,1239,"case <STR_LIT> : return expandReadSpecialRegisters ( MBB , MBBI , <NUM_LIT> ) ;"
LLVM,RISCV,1240,return true;
LLVM,RISCV,1241,}
LLVM,RISCV,1242,"BuildMI(NewMBB, DL, TII->get(<STR_LIT_2>), TmpReg).addReg(Symbol).addFrameIndex(<NUM_LIT>).addImm(FlagsHi);"
LLVM,RISCV,1243,"<ISA_LIT>ExpandPseudo :: expandCapStoreGlobalCap ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , MachineBasicBlock :: iterator & NextMBBI );"
LLVM,RISCV,1244,"return expandAuipcInstPair (MBB, MBBI, NextMBBI, <STR_LIT>, SecondOpcode, select);"
LLVM,RISCV,1245,
LLVM,RISCV,1246,"<ISA_LIT>LLT NextWidth = MRI.getType(LLT, Index).changeElementType(EltTy);"
LLVM,RISCV,1247,
LLVM,RISCV,1248,
LLVM,RISCV,1249,assert ( LMUL == <NUM_LIT> && <STR_LIT> ) ;
LLVM,RISCV,1250,MBBI -> eraseFromParent ( ) ;
LLVM,RISCV,1251,
LLVM,RISCV,1252,Unsupported binop;
LLVM,RISCV,1253,
LLVM,RISCV,1254,LoopTailMBB.insert(MI);
LLVM,RISCV,1255,Add a new case for AtomicRMWInst::UMax and AtomicRMWInst::UMin to handle unsigned operations.
LLVM,RISCV,1256,
LLVM,RISCV,1257,NewMBB->addSuccessor(&NewMBB);
LLVM,RISCV,1258,return false;
LLVM,RISCV,1259,"return expandVRESTORE ( MBB , MBBI ) ;"
LLVM,RISCV,1260,"Desc.expandLoadStoreMultipleOps(Opcode, MBBI->getOperand(0).getReg(), MBBI->getOperand(0).getReg(), MBBI->getOperand(1).getImm());"
LLVM,RISCV,1261,
LLVM,RISCV,1262,
LLVM,RISCV,1263,
LLVM,RISCV,1264,"return expandVSPILL ( MBB , MBBI ) ;"
LLVM,RISCV,1265,
LLVM,RISCV,1266,"BuildMI( MBB, MBBI, DL, Desc ).addReg( DstReg, RegState::Define | getDeadRegState( DstIsDead ) ).add( MBBI -> getOperand( <NUM_LIT> ) ).add( MBBI -> getOperand( <NUM_LIT> ) ).add( MBBI -> getOperand( <NUM_LIT> ) ) ;"
LLVM,RISCV,1267,
LLVM,RISCV,1268,
LLVM,RISCV,1269,
LLVM,RISCV,1270,"return expandAtomicCmpXchg(MBB, MBBI, true, <NUM_LIT>, NextMBBI);"
LLVM,RISCV,1271,else assert ( LMUL == <NUM_LIT> && <STR_LIT> ) ;
LLVM,RISCV,1272,MBBI->eraseFromParent ();
LLVM,RISCV,1273,
LLVM,RISCV,1274,
LLVM,RISCV,1275,unsigned MaskedReg = MI.getOperand(<NUM_LIT>).getReg();
LLVM,RISCV,1276,MBB.addSuccessor(DoneMBB);
LLVM,RISCV,1277,"insertMaskedMerge ( TII , DL , LoopTailMBB , ScratchReg , DestReg , NewValReg , MaskReg , ScratchReg ) ;"
LLVM,RISCV,1278,"BuildMI(LoopHeadMBB, DL, TII->get(<STR_LIT>)).addReg(DestReg).addReg(NewValReg).addMBB(DoneMBB);"
LLVM,RISCV,1279,
LLVM,RISCV,1280,
LLVM,RISCV,1281,"BuildMI ( MBB , DL , TII -> get ( MaskReg ), ScratchReg ) . addReg ( ScratchReg ) . addReg ( OldValReg ) ;"
LLVM,RISCV,1282,
LLVM,RISCV,1283,
LLVM,RISCV,1284,}
LLVM,RISCV,1285,"BuildMI(LoopMBB, DL, TII->get(<STR_LIT>)).addReg(ScratchReg).addReg(MaskReg);"
LLVM,RISCV,1286,.appendReg(ScratchReg);
LLVM,RISCV,1287,"case <STR_LIT> : return expandAtomicCmpXchg ( MBB , MBBI , AtomicRMWInst :: Xor , atomic <= 16 bits , <NUM_LIT> , NextMBBI ) ;"
LLVM,RISCV,1288,
LLVM,RISCV,1289,"return expandAtomicBinOp ( MBB , MBBI , AtomicRMWInst :: Star, true , <NUM_LIT> , NextMBBI ) ;"
LLVM,RISCV,1290,return false;
LLVM,RISCV,1291,}
LLVM,RISCV,1292,return new ExpandPseudoPass();
LLVM,RISCV,1293,
LLVM,RISCV,1294,IF(MF->getTarget().getCodeModel() == CodeModel::Small) {
LLVM,RISCV,1295,
LLVM,RISCV,1296,
LLVM,RISCV,1297,
LLVM,RISCV,1298,
LLVM,RISCV,1299,if (Subtarget.isELF()) {
LLVM,RISCV,1300,return Modified;
LLVM,RISCV,1301,
LLVM,RISCV,1302,
LLVM,RISCV,1303,
LLVM,RISCV,1304,
LLVM,RISCV,1305,}
LLVM,RISCV,1306,
LLVM,RISCV,1307,}
LLVM,RISCV,1308,return Modified;
LLVM,RISCV,1309,if (<ISA_LIT>FI -> getCallsEhReturn ( ) ) {
LLVM,RISCV,1310,return  EHDataReg[I];
LLVM,RISCV,1311,MF.getRegInfo().setPhysRegUsed(SP);
LLVM,RISCV,1312,}
LLVM,RISCV,1313,"BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)).addCFIIndex(CFIIndex).addImm(StackSize);"
LLVM,RISCV,1314,
LLVM,RISCV,1315,return MFI->getMaxCallFrameSize() + getStackAlignment() == 0;
LLVM,RISCV,1316,
LLVM,RISCV,1317,
LLVM,RISCV,1318,return nullptr;
LLVM,RISCV,1319,return ;
LLVM,RISCV,1320,Register ScratchReg = MRI.createVirtualRegister(&VRM::GPR64RegClass);
LLVM,RISCV,1321,
LLVM,RISCV,1322,
LLVM,RISCV,1323,Align RVVStackAlign (Offset) ;
LLVM,RISCV,1324,
LLVM,RISCV,1325,
LLVM,RISCV,1326,
LLVM,RISCV,1327,
LLVM,RISCV,1328,}
LLVM,RISCV,1329,
LLVM,RISCV,1330,The assertion statement assert (SecondSPAdjustAmount > 0 && <STR_LIT>) ;
LLVM,RISCV,1331,
LLVM,RISCV,1332,}
LLVM,RISCV,1333,
LLVM,RISCV,1334,continue;
LLVM,RISCV,1335,if ( RVFI->getLibCallStackSize() ) {
LLVM,RISCV,1336,return STI.getCpu();
LLVM,RISCV,1337,}
LLVM,RISCV,1338,}
LLVM,RISCV,1339,return RestoreLibCalls [ LibCallID ];
LLVM,RISCV,1340,return (SpillLibCalls[MF.getPort()]);
LLVM,RISCV,1341,
LLVM,RISCV,1342,
LLVM,RISCV,1343,
LLVM,RISCV,1344,return getTargetMachine().getDataLayout()->isIllegalVectorType(VT) ? TargetStackID::ScalableVectorFrame : TargetStackID::Default;
LLVM,RISCV,1345,
LLVM,RISCV,1346,
LLVM,RISCV,1347,
LLVM,RISCV,1348,return RegInfo->hasStackRealignment(MF) || MFI.hasVarSizedObjects() || MFI.isFrameAddressTaken();
LLVM,RISCV,1349,
LLVM,RISCV,1350,return MF.getSubtarget<llvm::SparcTargetLowering> (). getFrameLowering()->hasReservedCallFrame(MF);
LLVM,RISCV,1351,
LLVM,RISCV,1352,
LLVM,RISCV,1353,
LLVM,RISCV,1354,
LLVM,RISCV,1355,
LLVM,RISCV,1356,case TargetStackID :: RegStack: return false;
LLVM,RISCV,1357,Size += Info.getCalleeSavedSize();
LLVM,RISCV,1358,assert(MI != MBB.begin() && Next statement);
LLVM,RISCV,1359,
LLVM,RISCV,1360,unsigned Opc2 = <STR_LIT> ;
LLVM,RISCV,1361,unsigned ScratchReg2 = MRI . createVirtualRegister ( & <STR_LIT> ) ;
LLVM,RISCV,1362,
LLVM,RISCV,1363,
LLVM,RISCV,1364,
LLVM,RISCV,1365,
LLVM,RISCV,1366,
LLVM,RISCV,1367,
LLVM,RISCV,1368,
LLVM,RISCV,1369,
LLVM,RISCV,1370,
LLVM,RISCV,1371,
LLVM,RISCV,1372,::Value return TargetStackID::Vector;
LLVM,RISCV,1373,
LLVM,RISCV,1374,
LLVM,RISCV,1375,}
LLVM,RISCV,1376,<SRC> setSSPStartOffset(0);
LLVM,RISCV,1377,return STI.getFrameLowering();
LLVM,RISCV,1378,FI++;
LLVM,RISCV,1379,
LLVM,RISCV,1380,
LLVM,RISCV,1381,
LLVM,RISCV,1382,if (FirstSPAdjustAmount) {
LLVM,RISCV,1383,}
LLVM,RISCV,1384,return;
LLVM,RISCV,1385,return;
LLVM,RISCV,1386,
LLVM,RISCV,1387,return false;
LLVM,RISCV,1388,}
LLVM,RISCV,1389,
LLVM,RISCV,1390,if (I != E) return false;
LLVM,RISCV,1391,if ( ! MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasStdExtV ( ) ) {
LLVM,RISCV,1392,assert (MI != MBB.begin() && RestoreLibCall);
LLVM,RISCV,1393,assert(!MI->getOperand(0).isReg());
LLVM,RISCV,1394,return Subtarget.suppressFrameGrowth() ? -64 : 0;
LLVM,RISCV,1395,return new <ISA_LIT>FrameLowering(STI);
LLVM,RISCV,1396,"use external symbol SpillLibCall with flags MachineInstr::FrameSetup, and also add any register in CS as a live in for MBB."
LLVM,RISCV,1397,int VRegSize = FrameSize / 2;
LLVM,RISCV,1398,
LLVM,RISCV,1399,Predicted:
LLVM,RISCV,1400,"adjustReg (MBB, MBBI, DL, SPReg, SPReg, StackSize, MachineInstr::FrameDestroy);"
LLVM,RISCV,1401,MFI.setMaxCallFrameSize(MaxCallSize);
LLVM,RISCV,1402,
LLVM,RISCV,1403,"adjustReg (MBB, LastFrameDestroy, DL, SPReg, SPReg, FirstSPAdjustAmount, MachineInstr::FrameDestroy);"
LLVM,RISCV,1404,"BuildMI (MBB, MBBI, DL, TII->get(<STR_LIT>), VR).addReg(SPReg).addImm(-1 * ShiftAmount);"
LLVM,RISCV,1405,}
LLVM,RISCV,1406,return CSI[StackSize % CSI.size()];
LLVM,RISCV,1407,
LLVM,RISCV,1408,Offset += MF . getFrameInfo ( ) . getStackSize ( ) ;
LLVM,RISCV,1409,
LLVM,RISCV,1410,RS.scavengeRegister(RS.getNextRegister());
LLVM,RISCV,1411,
LLVM,RISCV,1412,The next statement may be something along the lines of: for (auto& B : MBB) {
LLVM,RISCV,1413,"CodeGenProcInstructions(MBB, MBBI, DL, RVFI, LastFrameDestroy, StackSize, RealStackSize);"
LLVM,RISCV,1414,unsigned SavedFPReg = <NUM_LIT> ;
LLVM,RISCV,1415,return -1;
LLVM,RISCV,1416,case <STR_LIT> : return <NUM_LIT> ;
LLVM,RISCV,1417,}
LLVM,RISCV,1418,if (MF.getFunction().hasFnAttribute(<STR_LIT>) && MFI.hasCalls()) {
LLVM,RISCV,1419,
LLVM,RISCV,1420,
LLVM,RISCV,1421,Offset += RVFI->getLibCallStackSize();
LLVM,RISCV,1422,
LLVM,RISCV,1423,auto * MF < <ISA_LIT>MachineFunction> = MF . getParent ( ) ;
LLVM,RISCV,1424,
LLVM,RISCV,1425,
LLVM,RISCV,1426,RS->addScavengingFrameIndex(RegScavFI);
LLVM,RISCV,1427,
LLVM,RISCV,1428,return SavedRegs;
LLVM,RISCV,1429,
LLVM,RISCV,1430,
LLVM,RISCV,1431,
LLVM,RISCV,1432,else return <STR_LIT> ;
LLVM,RISCV,1433,int FrameIdx = Info . getFrameIdx ( ) ;
LLVM,RISCV,1434,}
LLVM,RISCV,1435,
LLVM,RISCV,1436,}
LLVM,RISCV,1437,(StackAlign > StackSize) ? StackAlign : StackSize
LLVM,RISCV,1438,
LLVM,RISCV,1439,FrameReg = RI -> getFrameRegister( MF );
LLVM,RISCV,1440,assert (hasFP(MF) && <STR_LIT>);
LLVM,RISCV,1441,}
LLVM,RISCV,1442,}
LLVM,RISCV,1443,return ;
LLVM,RISCV,1444,
LLVM,RISCV,1445,
LLVM,RISCV,1446,
LLVM,RISCV,1447,}
LLVM,RISCV,1448,"BuildMI (MBB, MBBI, DL, TII -> get(TargetOpcode :: CFI_INSTRUCTION)). addCFIIndex (CFIIndex);"
LLVM,RISCV,1449,MF.getMachineFunction().getFunction().getName()
LLVM,RISCV,1450,MachineFrameInfo & MFI = MF.getFrameInfo();
LLVM,RISCV,1451,"BuildMI ( MBB , MBBI , DL , TII -> get ( Opc ) , Reg ) . addReg ( FactorRegister , RegState :: Kill ) .addReg(SPReg).addReg(FactorRegister, RegState:: Kill);"
LLVM,RISCV,1452,
LLVM,RISCV,1453,uint64_t FPOffset = RealStackSize - RVFI -> getVarArgsSaveSize ( ) ;
LLVM,RISCV,1454,"adjustReg(MBB, LastFrameDestroy, DL, SPReg, FPReg, FPOffset - FirstSPAdjustAmount, MachineInstr::FrameDestroy);"
LLVM,RISCV,1455,MachineRegisterInfo & MRI = MF . getRegInfo ( ) ;
LLVM,RISCV,1456,
LLVM,RISCV,1457,
LLVM,RISCV,1458,}
LLVM,RISCV,1459,
LLVM,RISCV,1460,
LLVM,RISCV,1461,
LLVM,RISCV,1462,
LLVM,RISCV,1463,
LLVM,RISCV,1464,"TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ;"
LLVM,RISCV,1465,}
LLVM,RISCV,1466,
LLVM,RISCV,1467,"uint64_t PrologueSaveSize = <some calculation using FrameSize, StackAlign, and MaxCallFrameSize> ;"
LLVM,RISCV,1468,
LLVM,RISCV,1469,if (MBBI != MBB.end()) {
LLVM,RISCV,1470,
LLVM,RISCV,1471,"Offset += StackOffset :: get ( MFI . getObjectOffset ( FI ) , RVFI -> getRVVStackSize ( ) ) ;"
LLVM,RISCV,1472,
LLVM,RISCV,1473,}
LLVM,RISCV,1474,
LLVM,RISCV,1475,
LLVM,RISCV,1476,
LLVM,RISCV,1477,}
LLVM,RISCV,1478,"BL = MBB, MBBI, DL, TII->get(Opcodes:: SUB_I_R), SPReg .addReg(SPReg).addImm(ShiftAmount)"
LLVM,RISCV,1479,"djp9oxOa, 3 && Stack realignment adjustment must be a power of two);"
LLVM,RISCV,1480,assert(!hasFP(MF));
LLVM,RISCV,1481,}
LLVM,RISCV,1482,
LLVM,RISCV,1483,
LLVM,RISCV,1484,
LLVM,RISCV,1485,return false;
LLVM,RISCV,1486,return true;
LLVM,RISCV,1487,return MFI . hasVarSizedObjects ( ) ;
LLVM,RISCV,1488,
LLVM,RISCV,1489,"Predict the next statement of this code snippet:  RegInfo . emitPrologue ( * MBB . getParent ( ) , MBB ) ;"
LLVM,RISCV,1490,}
LLVM,RISCV,1491,
LLVM,RISCV,1492,
LLVM,RISCV,1493,Return FrameSize + MaxCallSize;
LLVM,RISCV,1494,
LLVM,RISCV,1495,"return adjustReg ( MBB , LastFrameDestroy , DL , SPReg , SPReg , FirstSPAdjustAmount , MachineInstr :: FrameSetup )"
LLVM,RISCV,1496,
LLVM,RISCV,1497,
LLVM,RISCV,1498,
LLVM,RISCV,1499,return;
LLVM,RISCV,1500,
LLVM,RISCV,1501,<NUM_LIT> = <NUM_LIT> - getStackAlign ( ) . value ( ) ;
LLVM,RISCV,1502,
LLVM,RISCV,1503,case <STR_LIT> : return <NUM_LIT> ;
LLVM,RISCV,1504,for (const CalleeSavedInfo & Info : CSI ) {
LLVM,RISCV,1505,return NonLibcallCSI ;
LLVM,RISCV,1506,likely going to use the TRI variable to access information about a specific target register using a function or method provided by the STI object. For example: unsigned int regSize = TRI->getRegSize(reg);
LLVM,RISCV,1507,return MFI .hasVariaibleSizedObjects() }
LLVM,RISCV,1115,<\ISA_LIT> bool isAddressValid = true;
LLVM,RISCV,1116,
LLVM,RISCV,1508,std::cout << Checking if the frame pointer is valid for this function... << std::endl;
LLVM,RISCV,1509,
LLVM,RISCV,1510,return MF.getFunction().hasFnAttribute(Attribute::AlwaysInline);
LLVM,RISCV,1511,
LLVM,RISCV,1512,
LLVM,RISCV,1513,
LLVM,RISCV,1514,
LLVM,RISCV,1515,}
LLVM,RISCV,1516,return true ;
LLVM,RISCV,1517,
LLVM,RISCV,1518,
LLVM,RISCV,1519,
LLVM,RISCV,1520,
LLVM,RISCV,1521,if (!L->isLoopInvariant(Step)) return false;
LLVM,RISCV,1522,
LLVM,RISCV,1523,"for ( auto * II : Scatters ) Changed |= tryCreateStridedLoadStore ( II , II -> getType ( ) , II -> getArgOperand ( <NUM_LIT> ) , II -> getArgOperand ( <NUM_LIT> ) ) ;"
LLVM,RISCV,1524,
LLVM,RISCV,1525,
LLVM,RISCV,1526,AU.setOption(EnableLoopVectorizer);
LLVM,RISCV,1527,
LLVM,RISCV,1528,
LLVM,RISCV,1529,ConstantInt * StartC = dyn_cast_or_null<ConstantInt>(StrideVal);
LLVM,RISCV,1530,return true;
LLVM,RISCV,1531,
LLVM,RISCV,1532,
LLVM,RISCV,1533,
LLVM,RISCV,1534,}
LLVM,RISCV,1535,
LLVM,RISCV,1536,return true;
LLVM,RISCV,1537,
LLVM,RISCV,1538,if (InstrInfo.MaskRegOp && InstrInfo.MulSel == MulSel && InstrInfo.ScaleMode == ScaleMode && this.N == InstrInfo.N) return true;
LLVM,RISCV,1539,Possible options: - Throw an error: Invalid assertion.
LLVM,RISCV,1540,"if (getMemOperand(DefMI, 1)->getSize() > Require.getVTYPE().getSize()) {"
LLVM,RISCV,1541,
LLVM,RISCV,1542,
LLVM,RISCV,1543,
LLVM,RISCV,1544,}
LLVM,RISCV,1545,}
LLVM,RISCV,1546,MachineBasicBlock * UseBB = PHI -> getParent ( ) ;
LLVM,RISCV,1547,VSETVLIInfo DefInfo = getInfoForVSETVLI(*DefMI);
LLVM,RISCV,1548,
LLVM,RISCV,1549,
LLVM,RISCV,1550,NeedInsertVSETVLI = false ;
LLVM,RISCV,1551,if (hasSameMaskOp(InstrInfo) && TailAgnostic == InstrInfo.TailAgnostic && MaskAgnostic == InstrInfo.MaskAgnostic) return true;
LLVM,RISCV,1552,
LLVM,RISCV,1553,
LLVM,RISCV,1554,
LLVM,RISCV,1555,return (this.SEW == Other.SEW);
LLVM,RISCV,1556,return false ;
LLVM,RISCV,1557,if ( isUnknown ( ) || InstrInfo . isUnknown ( ) ) return false ;
LLVM,RISCV,1558,
LLVM,RISCV,1559,
LLVM,RISCV,1560,}
LLVM,RISCV,1561,
LLVM,RISCV,1562,
LLVM,RISCV,1563,
LLVM,RISCV,1564,
LLVM,RISCV,1565,
LLVM,RISCV,1566,if (isBundle(MI)) {
LLVM,RISCV,1567,
LLVM,RISCV,1568,if (SEW == InstrInfo.SEW) return true;
LLVM,RISCV,1569,
LLVM,RISCV,1570,
LLVM,RISCV,1571,assert( sizeof(T) == datalayout.getSizeOfByteAddr());
LLVM,RISCV,1572,
LLVM,RISCV,1573,if ( hasOtherSEWMatching () ) return false;
LLVM,RISCV,1574,
LLVM,RISCV,1575,
LLVM,RISCV,1576,throw new UnsupportedOperationException(Unsupported AVLImm.);
LLVM,RISCV,1577,
LLVM,RISCV,1578,TailAgnostic = true;
LLVM,RISCV,1579,StoreOp = MI.getNumExplicitDefs() == <NUM_LIT> ;
LLVM,RISCV,1580,}
LLVM,RISCV,1581,
LLVM,RISCV,1582,}
LLVM,RISCV,1583,}
LLVM,RISCV,1584,
LLVM,RISCV,1585,if ( MI . getOpcode ( ) == VSETVLI ) {
LLVM,RISCV,1586,
LLVM,RISCV,1587,print (dbgs()) ;
LLVM,RISCV,1588,
LLVM,RISCV,1589,}
LLVM,RISCV,1590,
LLVM,RISCV,1591,}
LLVM,RISCV,1592,}
LLVM,RISCV,1593,}
LLVM,RISCV,1594,else return false;
LLVM,RISCV,1595,}
LLVM,RISCV,1596,if (ST.hasVL()) return true;
LLVM,RISCV,1597,
LLVM,RISCV,1598,return false;
LLVM,RISCV,1599,
LLVM,RISCV,1600,
LLVM,RISCV,1601,return false ;
LLVM,RISCV,1602,return true;
LLVM,RISCV,1603,return false;
LLVM,RISCV,1604,if (hasAVLCall()) OS << <STR_LIT> << (unsigned)AVLCall;
LLVM,RISCV,1605,MI . getOperand ( 1 ) . setImm ( Pred ) ;
LLVM,RISCV,1606,
LLVM,RISCV,1607,
LLVM,RISCV,1608,
LLVM,RISCV,1609,
LLVM,RISCV,1610,
LLVM,RISCV,1611,"return <ISA_LIT>VType :: encodeVTYPE ( VLMul , SEW , TailAgnostic , MaskAgnostic ) ;"
LLVM,RISCV,1612,
LLVM,RISCV,1613,return this->VTYPE == Other.VTYPE;
LLVM,RISCV,1614,if (HasAVL) {
LLVM,RISCV,1615,return Other;
LLVM,RISCV,1616,return <STR_LIT> ( ) ;
LLVM,RISCV,1617,
LLVM,RISCV,1618,
LLVM,RISCV,1619,
LLVM,RISCV,1620,
LLVM,RISCV,1621,return VSETVLIInfo initialized with AVLImm value <NUM_LIT>;
LLVM,RISCV,1622,
LLVM,RISCV,1623,}
LLVM,RISCV,1624,Register AVLReg = Info.getAVLReg();
LLVM,RISCV,1625,
LLVM,RISCV,1626,
LLVM,RISCV,1627,Return false;
LLVM,RISCV,1628,
LLVM,RISCV,1629,
LLVM,RISCV,1630,
LLVM,RISCV,1631,BlockData ( ) {
LLVM,RISCV,1632,
LLVM,RISCV,1633,
LLVM,RISCV,1634,}
LLVM,RISCV,1635,
LLVM,RISCV,1636,
LLVM,RISCV,1637,
LLVM,RISCV,1638,return nullptr;
LLVM,RISCV,1639,
LLVM,RISCV,1640,assert ( BlockInfo [ MBB . getNumber ( ) ] . Pred . isValid ( ) && <STR_LIT> ) ;
LLVM,RISCV,1641,
LLVM,RISCV,1642,
LLVM,RISCV,1643,}
LLVM,RISCV,1644,
LLVM,RISCV,1645,assert ( NewInfo . getAVLReg ( ) == AVLReg ) ;
LLVM,RISCV,1646,
LLVM,RISCV,1647,}
LLVM,RISCV,1648,
LLVM,RISCV,1649,
LLVM,RISCV,1650,assert ( isValid ( ) && ! isUnknown ( ) && <STR_LIT> ) ;
LLVM,RISCV,1651,
LLVM,RISCV,1652,}
LLVM,RISCV,1653,}
LLVM,RISCV,1654,
LLVM,RISCV,1655,
LLVM,RISCV,1656,
LLVM,RISCV,1657,return (VLMAX == Other.getVLMAX());
LLVM,RISCV,1658,
LLVM,RISCV,1659,<STR_LIT> ) ;
LLVM,RISCV,1660,
LLVM,RISCV,1661,
LLVM,RISCV,1662,if (Other.getVlen() > this->getVlen()) {
LLVM,RISCV,1663,if (TailAgnostic != InstrInfo.TailAgnostic || MaskAgnostic != InstrInfo.MaskAgnostic) return false;
LLVM,RISCV,1664,
LLVM,RISCV,1665,
LLVM,RISCV,1666,
LLVM,RISCV,1667,return true;
LLVM,RISCV,1668,
LLVM,RISCV,1669,
LLVM,RISCV,1670,
LLVM,RISCV,1671,
LLVM,RISCV,1672,if ( ! PBB || PBB -> empty ( ) ) return true ;
LLVM,RISCV,1673,
LLVM,RISCV,1674,}
LLVM,RISCV,1675,assert(BlockInfo.empty() && <STR_LIT>);
LLVM,RISCV,1676,}
LLVM,RISCV,1677,
LLVM,RISCV,1678,
LLVM,RISCV,1679,}
LLVM,RISCV,1680,}
LLVM,RISCV,1681,
LLVM,RISCV,1682,
LLVM,RISCV,1683,
LLVM,RISCV,1684,O <<  =  << Register[Base] ;
LLVM,RISCV,1685,}
LLVM,RISCV,1686,
LLVM,RISCV,1687,}
LLVM,RISCV,1688,}
LLVM,RISCV,1689,}
LLVM,RISCV,1690,
LLVM,RISCV,1691,if ( Offset < <NUM_LIT> ) OS << '-' ;
LLVM,RISCV,1692,
LLVM,RISCV,1693,return;
LLVM,RISCV,1694,}
LLVM,RISCV,1695,OS << getRegisterName ( MI -> getOperand( opNum + 1 ) . getReg ( ) ) ;
LLVM,RISCV,1696,
LLVM,RISCV,1697,
LLVM,RISCV,1698,
LLVM,RISCV,1699,}
LLVM,RISCV,1700,
LLVM,RISCV,1701,
LLVM,RISCV,1702,
LLVM,RISCV,1703,
LLVM,RISCV,1704,
LLVM,RISCV,1705,
LLVM,RISCV,1706,}
LLVM,RISCV,1707,
LLVM,RISCV,1708,}
LLVM,RISCV,1709,
LLVM,RISCV,1710,O << MO.getReg() ;
LLVM,RISCV,1711,}
LLVM,RISCV,1712,
LLVM,RISCV,1713,}
LLVM,RISCV,1714,
LLVM,RISCV,1715,
LLVM,RISCV,1716,
LLVM,RISCV,1717,if ( Res ) NewMI = const_cast < MCInst * > ( & UncompressedMI ) ;
LLVM,RISCV,1718,
LLVM,RISCV,1719,unsigned Imm = MI->getOperand(OpNo).getImm();
LLVM,RISCV,1720,
LLVM,RISCV,1721,return false ;
LLVM,RISCV,1722,
LLVM,RISCV,1723,if ( ( FenceArg & <STR_LIT> ) != <NUM_LIT> ) O << 'o' ;
LLVM,RISCV,1724,"printAnnotation ( O , Annot ) ;"
LLVM,RISCV,1725,UncompressedMI = *NewMI.
LLVM,RISCV,1726,}
LLVM,RISCV,1727,if ( PrintHex <VTypeI > ) O <<  0x << hex << Imm << ( <ISA_LIT> ) }
LLVM,RISCV,1728,"Given the previous statement, the next statement would be O << ISA_LIT;"
LLVM,RISCV,1729,NewMI = const_cast < MCInst * > (MI);
LLVM,RISCV,1730,"printRegName ( O , MO . getReg ( ) ) ;"
LLVM,RISCV,1731,
LLVM,RISCV,1732,
LLVM,RISCV,1733,Ediv = <NUM_LIT> << Ediv ;
LLVM,RISCV,1734,}
LLVM,RISCV,1735,"printInstruction(MI, O);"
LLVM,RISCV,1736,O << <STR_LIT> ;
LLVM,RISCV,1737,Else if ( MC .isFPImm ( ) ) O << MC .getFPImm ( ) ;
LLVM,RISCV,1738,
LLVM,RISCV,1739,
LLVM,RISCV,1740,
LLVM,RISCV,1741,if (Value >= 0) {
LLVM,RISCV,1742,
LLVM,RISCV,1743,
LLVM,RISCV,1744,}
LLVM,RISCV,1745,O << Value;
LLVM,RISCV,1746,O << 'u' ;
LLVM,RISCV,1747,
LLVM,RISCV,1748,
LLVM,RISCV,1749,null;
LLVM,RISCV,1750,return ArchRegNames;
LLVM,RISCV,1751,"Based on the pattern of the code, the next statement is expected to end with a semicolon (;"
LLVM,RISCV,1752,}
LLVM,RISCV,1753,
LLVM,RISCV,1754,
LLVM,RISCV,1755,O << 'w' ;
LLVM,RISCV,1756,
LLVM,RISCV,1757,
LLVM,RISCV,1758,
LLVM,RISCV,1759,
LLVM,RISCV,1760,"printImmValue(O, MO.getImm());"
LLVM,RISCV,1761,}
LLVM,RISCV,1762,
LLVM,RISCV,1763,
LLVM,RISCV,1764,
LLVM,RISCV,1765,
LLVM,RISCV,1766,return MIB . addImm ( Offset ) . addFrameIndex ( FI ) . addMemOperand ( MMO ) ;
LLVM,RISCV,1767,}
LLVM,RISCV,1768,
LLVM,RISCV,1769,if(I!=MBB.end()) : TBB = ThisTarget -> getMBB();
LLVM,RISCV,1770,}
LLVM,RISCV,1771,case <TRIPLE_LIT>LXZX: return expandLXZX( MI );
LLVM,RISCV,1772,
LLVM,RISCV,1773,STI.getABIName();
LLVM,RISCV,1774,
LLVM,RISCV,1775,return Opcode ;
LLVM,RISCV,1776,
LLVM,RISCV,1777,"BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( FBB ) ;"
LLVM,RISCV,1778,
LLVM,RISCV,1779,"BuildMI(MBB, I, DL, get(<STR_LIT>)).addMBB(FBB).addImm(1).addReg(Cond[<NUM_LIT>].getReg()).addReg(Cond[<NUM_LIT>].getReg());"
LLVM,RISCV,1780,
LLVM,RISCV,1781,
LLVM,RISCV,1782,The next statement could potentially be a closing }
LLVM,RISCV,1783,
LLVM,RISCV,1784,
LLVM,RISCV,1785,}
LLVM,RISCV,1786,
LLVM,RISCV,1787,
LLVM,RISCV,1788,continue;
LLVM,RISCV,1789,
LLVM,RISCV,1790,
LLVM,RISCV,1791,"getLoadStoreOpcodes ( RC , LoadOpcode , StoreOpcode ) ;"
LLVM,RISCV,1792,}
LLVM,RISCV,1793,int HighWidth = ( HighOffset == OffsetB ) ? WidthB : WidthA ;
LLVM,RISCV,1794,return LowOffset + WidthA >= HighOffset ;
LLVM,RISCV,1795,MBB . addLiveOut ( <STR_LIT> ) ;
LLVM,RISCV,1796,
LLVM,RISCV,1797,
LLVM,RISCV,1798,
LLVM,RISCV,1799,Opc = <STR_LIT> ;
LLVM,RISCV,1800,
LLVM,RISCV,1801,
LLVM,RISCV,1802,<e>return NumOp;
LLVM,RISCV,1803,
LLVM,RISCV,1804,
LLVM,RISCV,1805,BaseReg = & LdSt.getOperand(<NUM_LIT>);
LLVM,RISCV,1806,
LLVM,RISCV,1807,
LLVM,RISCV,1808,return MCInstBuilder (<STR_LIT>).addReg (<STR_LIT>).addReg (<STR_LIT>).addImm (<NUM_LIT>).addReg (<STR_LIT>);
LLVM,RISCV,1809,default: return Invalid input;
LLVM,RISCV,1810,outliner::Candidate &C = RepeatedSequenceLocs;
LLVM,RISCV,1811,
LLVM,RISCV,1812,{
LLVM,RISCV,1813,std::cout << Target flags initialized. << std::endl;
LLVM,RISCV,1814,
LLVM,RISCV,1815,return VL;
LLVM,RISCV,1816,
LLVM,RISCV,1817,RS -> enterBasicBlockEnd ( MBB ) ;
LLVM,RISCV,1818,return <NUM_LIT> ;
LLVM,RISCV,1819,
LLVM,RISCV,1820,
LLVM,RISCV,1821,"return isIntN ( <NUM_LIT> , BrOffset ) ;"
LLVM,RISCV,1822,return BrOffset >= - <ISA_LIT> && BrOffset < <ISA_LIT> ;
LLVM,RISCV,1823,
LLVM,RISCV,1824,return DestSourcePair {
LLVM,RISCV,1825,
LLVM,RISCV,1826,if (F.hasPersonality()) return false;
LLVM,RISCV,1827,
LLVM,RISCV,1828,return false;
LLVM,RISCV,1829,"return ! CheckFIs || any_of ( MI . operands ( ) , [ ] ( const MachineOperand & MO ) {"
LLVM,RISCV,1830,return MO.getType() == MachineOperand::MO_FPImmediate;
LLVM,RISCV,1831,
LLVM,RISCV,1832,
LLVM,RISCV,1833,}
LLVM,RISCV,1834,return 0;
LLVM,RISCV,1835,if (IsZvlsseg) {
LLVM,RISCV,1836,llvm_unreachable ( <STR_LIT> ) ;
LLVM,RISCV,1837,}
LLVM,RISCV,1838,else {
LLVM,RISCV,1839,if (Target->succ_empty()) {
LLVM,RISCV,1840,else I->eraseFromParent();
LLVM,RISCV,1841,return <NUM_LIT>;
LLVM,RISCV,1842,
LLVM,RISCV,1843,return new InstrInfo(STI);
LLVM,RISCV,1844,return new InstrInfo();
LLVM,RISCV,1845,Opcode = <STR_LIT> ;
LLVM,RISCV,1846,if (STI.getTargetTriple().isArch64Bit()) Ok = isInt<<<NUM_LIT>>>(Imm);
LLVM,RISCV,1847,break ;
LLVM,RISCV,1848,"BuildMI(MBB, MBBI, DL, get(Opc), DstReg).addReg(SrcReg, getKillRegState(KillSrc)).addReg(SrcReg, getKillRegState(KillSrc));"
LLVM,RISCV,1849,{
LLVM,RISCV,1850,for (auto &C : RepeatedSequenceLocs) {
LLVM,RISCV,1851,if (MI.isCall()) return outliner::InstrType::Illegal;
LLVM,RISCV,1852,
LLVM,RISCV,1853,if (BytesAdded) * BytesAdded += getInstSizeInBytes(CondMI);
LLVM,RISCV,1854,
LLVM,RISCV,1855,
LLVM,RISCV,1856,
LLVM,RISCV,1857,
LLVM,RISCV,1858,"BuildMI ( MBB , I , DL , get ( Opcode ) , DstReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ;"
LLVM,RISCV,1859,Opcode += <STR_LIT> ;
LLVM,RISCV,1860,.setMIFlag(Flag);
LLVM,RISCV,1861,<p>Return Result;
LLVM,RISCV,1862,
LLVM,RISCV,1863,MIB.add(MI.getOperand(<NUM_LIT>));
LLVM,RISCV,1864,}
LLVM,RISCV,1865,"<STR_LIT> ( Val , STI . getFeatureBits ( ) ) ;"
LLVM,RISCV,1866,"BuildMI ( MBB , MBBI , DL , get ( Inst . Opc ) , Result ) . addReg ( SrcReg , RegState :: Kill ) . addImm ( Inst . Imm ) . setMIFlag ( Flag ) ;"
LLVM,RISCV,1867,if (STI.getTargetTriple().isArch64Bit()) Ok = isUInt <<NUM_LIT>> (Imm) ;
LLVM,RISCV,1868,
LLVM,RISCV,1869,evaluate the safety of outlining MBB with the given flags using the TargetInstrInfo::isMBBSafeToOutlineFrom function and return the result.
LLVM,RISCV,1870,
LLVM,RISCV,1871,}
LLVM,RISCV,1872,"LIS -> ReplaceMachineInstrInMaps ( MI , * MIB ) ;"
LLVM,RISCV,1873,
LLVM,RISCV,1874,
LLVM,RISCV,1875,II = MBB.begin();
LLVM,RISCV,1876,
LLVM,RISCV,1877,
LLVM,RISCV,1878,"BuildMI (MBB, I, DL, get(Opcode), DstReg).addFrameIndex(FI).addImm(<NUM_LIT>);"
LLVM,RISCV,1879,): return;
LLVM,RISCV,1880,
LLVM,RISCV,1881,
LLVM,RISCV,1882,
LLVM,RISCV,1883,}
LLVM,RISCV,1884,
LLVM,RISCV,1885,"MBB.insert(I, addReg(DstReg, FI, RC));"
LLVM,RISCV,1886,if (DL.isValid()) I++;
LLVM,RISCV,1887,return <NUM_LIT>;
LLVM,RISCV,1888,
LLVM,RISCV,1889,MMO->getOffset();
LLVM,RISCV,1890,}
LLVM,RISCV,1891,a conditional statement that checks if the condition stated in the previous line is true or false. It could be something like: if (DstReg > SrcReg && (DstReg - SrcReg) < NumRegs) {
LLVM,RISCV,1892,break;
LLVM,RISCV,1893,
LLVM,RISCV,1894,"BuildMI (MBB, MBBI, DL, get(Inst.Opc), Result).addReg(SrcReg, RegState::Kill).addImm(0)"
LLVM,RISCV,1895,`break;
LLVM,RISCV,1896,
LLVM,RISCV,1897,
LLVM,RISCV,1898,RS -> enterBasicBlockEnd(MBB);
LLVM,RISCV,1899,return It ;
LLVM,RISCV,1900,
LLVM,RISCV,1901,}
LLVM,RISCV,1902,
LLVM,RISCV,1903,"BuildMI (MBB, MBBI, DL, get (Inst.Opc), DstReg).addImm (Inst.Imm).setMIFlag (Flag);"
LLVM,RISCV,1904,
LLVM,RISCV,1905,SubRegIdx = <STR_LIT> ;
LLVM,RISCV,1906,
LLVM,RISCV,1907,
LLVM,RISCV,1908,return outliner :: InstrType :: Illegal ;
LLVM,RISCV,1909,Register N = MRI . createVirtualRegister ( & <STR_LIT> ) ;
LLVM,RISCV,1910,Unable to encode scaled RC instruction size in ADD/sub immediate . }
LLVM,RISCV,1911,break ;
LLVM,RISCV,1912,
LLVM,RISCV,1913,return false;
LLVM,RISCV,1914,RVFI->setHasSpillVRs();
LLVM,RISCV,1915,is<ISA_LIT>Vector = true ;
LLVM,RISCV,1916,NF = <NUM_LIT> ;
LLVM,RISCV,1917,return None ;
LLVM,RISCV,1918,`None;
LLVM,RISCV,1919,the ending curly bracket (}
LLVM,RISCV,1920,MO_CCALL }
LLVM,RISCV,1921,}
LLVM,RISCV,1922,MBB . addSuccessor ( TBB ) ;
LLVM,RISCV,1923,MI.eraseFromParent():.
LLVM,RISCV,1924,
LLVM,RISCV,1925,return MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;
LLVM,RISCV,1926,case <STR_LIT> :
LLVM,RISCV,1927,<NUM_LIT> ;
LLVM,RISCV,1928,
LLVM,RISCV,1929,return getRegisterInfo ( ) -> <STR_LIT> ;
LLVM,RISCV,1930,
LLVM,RISCV,1931,Opcode = <STR_LIT> ;
LLVM,RISCV,1932,
LLVM,RISCV,1933,
LLVM,RISCV,1934,
LLVM,RISCV,1935,Opcode = <STR_LIT> ;
LLVM,RISCV,1936,return <NUM_LIT> ;
LLVM,RISCV,1937,return false ;
LLVM,RISCV,1938,return false ;
LLVM,RISCV,1939,"return isIntN ( <NUM_LIT> , BrOffset ) ;"
LLVM,RISCV,1940,return true;
LLVM,RISCV,1941,
LLVM,RISCV,1942,case <STR_LIT> : Ok = isRelativeBranch < <NUM_LIT> > ( Imm ) ;
LLVM,RISCV,1943,I -> removeFromParent ();
LLVM,RISCV,1944,
LLVM,RISCV,1945,".addReg(SrcReg, getKillRegState(KillSrc));"
LLVM,RISCV,1946,"return getInlineAsmLength (MI.getOperand(<NUM_LIT>).getSymbolName(), *TM.getMCAsmInfo());"
LLVM,RISCV,1947,
LLVM,RISCV,1948,
LLVM,RISCV,1949,
LLVM,RISCV,1950,
LLVM,RISCV,1951,
LLVM,RISCV,1952,if (I != MBB.end()) DL = I->getDebugLoc();
LLVM,RISCV,1953,
LLVM,RISCV,1954,else DL = DebugLoc ( );
LLVM,RISCV,1955,debugInfo << saving register  << TRI->getName(SrcReg) <<  into frame index  << FI ;
LLVM,RISCV,1956,return <NUM_LIT> ;
LLVM,RISCV,1957,}
LLVM,RISCV,1958,
LLVM,RISCV,1959,
LLVM,RISCV,1960,assert ( isInt < <NUM_LIT> > ( NumOfVReg ) && <STR_LIT> ) ;
LLVM,RISCV,1961,
LLVM,RISCV,1962,
LLVM,RISCV,1963,}
LLVM,RISCV,1964,<STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ;
LLVM,RISCV,1965,}
LLVM,RISCV,1966,llvm_unreachable( <STR_LIT> );
LLVM,RISCV,1967,MBB.addCaptureInfo(Opcode);
LLVM,RISCV,1968,
LLVM,RISCV,1969,
LLVM,RISCV,1970,else if (<STR_LIT>.hasSubClassEq(RC)) Opcode = <STR_LIT>;
LLVM,RISCV,1971,"BuildMI (MBB, MBBI, DL, get(Inst.Opc), Result).addReg(SrcReg, RegState::Kill).addReg(SrcReg, RegState::Kill).setMIFlag(Flag);"
LLVM,RISCV,1972,"BuildMI ( MBB , MBBI <STR{"
LLVM,RISCV,1973,
LLVM,RISCV,1974,
LLVM,RISCV,1975,return None;
LLVM,RISCV,1976,break;
LLVM,RISCV,1977,assert(TBB);
LLVM,RISCV,1978,}
LLVM,RISCV,1979,return ;
LLVM,RISCV,1980,return false ;
LLVM,RISCV,1981,}
LLVM,RISCV,1982,
LLVM,RISCV,1983,"case <STR_LIT> : BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) .addMBB ( TBB ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) .addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) ;"
LLVM,RISCV,1984,execute llvm_unreachable(<STR_LIT>);
LLVM,RISCV,1985,
LLVM,RISCV,1986,}
LLVM,RISCV,1987,}
LLVM,RISCV,1988,
LLVM,RISCV,1989,return <STR_LIT> ;
LLVM,RISCV,1990,
LLVM,RISCV,1991,return false ;
LLVM,RISCV,1992,
LLVM,RISCV,1993,"Retrieve the high 20 bits of Val and bit-shift them by 16, storing the result in Hi20. Then, retrieve the low 12 bits and sign extend them by shifting them by 16, storing the result in Lo12. Finally, use the BuildMI function to build the instruction, passing in the MachineBasicBlock, MachineBasicBlock::iterator, DebugLoc, and register DstReg as arguments. Add the immediate value Hi20 to the instruction and set the MIFlag to Flag."
LLVM,RISCV,1994,a closing bracket (}
LLVM,RISCV,1995,
LLVM,RISCV,1996,
LLVM,RISCV,1997,
LLVM,RISCV,1998,
LLVM,RISCV,1999,
LLVM,RISCV,2000,
LLVM,RISCV,2001,return a numerical literal. }
LLVM,RISCV,2002,return <NUM_LIT> ;
LLVM,RISCV,2003,}
LLVM,RISCV,2004,The code is likely inside a function and the next statement could be  }
LLVM,RISCV,2005,return <STR_LIT> ;
LLVM,RISCV,2006,
LLVM,RISCV,2007,
LLVM,RISCV,2008,
LLVM,RISCV,2009,FrameIndex = MI.getOperand(<NUM_LIT>).getIndex();
LLVM,RISCV,2010,
LLVM,RISCV,2011,return Opcode;
LLVM,RISCV,2012,llvm_unreachable(<STR_LIT>);
LLVM,RISCV,2013,"BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) , DstReg ) . addImm ( Lo12 ) . setMIFlag ( Flag ) ;"
LLVM,RISCV,2014,Cond .back() = MachineOperand::CreateImm(Target) ;
LLVM,RISCV,2015,Cond . getOperand ( <NUM_LIT> ) ;
LLVM,RISCV,2016,return <NUM_LIT>;
LLVM,RISCV,2017,
LLVM,RISCV,2018,
LLVM,RISCV,2019,
LLVM,RISCV,2020,
LLVM,RISCV,2021,__InstrInfo_print ( ) ;
LLVM,RISCV,2022,llvm_unreachable ( <STR_LIT> ) ;
LLVM,RISCV,2023,llvm_unreachable (<STR_LIT>);
LLVM,RISCV,2024,
LLVM,RISCV,2025,
LLVM,RISCV,2026,"return new ISA_LITInstructionSelector(TM, Subtarget, RBI);"
LLVM,RISCV,2027,
LLVM,RISCV,2028,
LLVM,RISCV,2029,}
LLVM,RISCV,2030,
LLVM,RISCV,2031,
LLVM,RISCV,2032,
LLVM,RISCV,2033,}
LLVM,RISCV,2034,
LLVM,RISCV,2035,}
LLVM,RISCV,2036,
LLVM,RISCV,2037,return IsBase ;
LLVM,RISCV,2038,return ;
LLVM,RISCV,2039,"return CurDAG->getTargetConstant(Imm, SDLoc(Node), Node->getValueType(nullptr));"
LLVM,RISCV,2040,
LLVM,RISCV,2041,
LLVM,RISCV,2042,
LLVM,RISCV,2043,return (Val == 0);
LLVM,RISCV,2044,
LLVM,RISCV,2045,
LLVM,RISCV,2046,"<ISA_LIT>AddressingMode ( AddrForm form , OffRange offr ) : Form ( form ) , OffR ( offr ) , Base ( ) , Offset ( <NUM_LIT> ) , Operand ( Operand ) ;"
LLVM,RISCV,2047,return return Subtarget.getTargetLowering();
LLVM,RISCV,2048,
LLVM,RISCV,2049,return ret;
LLVM,RISCV,2050,}
LLVM,RISCV,2051,Counter;
LLVM,RISCV,2052,OutOps . push_back ( Op ) ;
LLVM,RISCV,2053,Base = Addr.getOperand(<NUM_LIT>);
LLVM,RISCV,2054,
LLVM,RISCV,2055,
LLVM,RISCV,2056,}
LLVM,RISCV,2057,if (Addr->getOpcode() != ISD::TargetConstant) {
LLVM,RISCV,2058,"if (Op1.getNode()) Lower = CurDAG -> getNode(Opcode, DL, VT, Op1, Lower);"
LLVM,RISCV,2059,
LLVM,RISCV,2060,<SYM_LIT> <SPACE> CurDAG -> init ( getTargetMachine ( ) ) ;
LLVM,RISCV,2061,}
LLVM,RISCV,2062,
LLVM,RISCV,2063,return N & ((1 << 5) - 1);
LLVM,RISCV,2064,
LLVM,RISCV,2065,
LLVM,RISCV,2066,
LLVM,RISCV,2067,<p> return true;
LLVM,RISCV,2068,return true;
LLVM,RISCV,2069,
LLVM,RISCV,2070,
LLVM,RISCV,2071,"return std::count(node->users().begin(), node->users().end(), this) == node.getNumOperands();"
LLVM,RISCV,2072,
LLVM,RISCV,2073,Position--;
LLVM,RISCV,2074,"CurDAG -> getMemIntrinsicNode ( <STR_LIT> , DL , VTs , Ops , <STR_LIT> , MPI , Align ( <NUM_LIT> ) , MachineMemOperand :: MOLoad )"
LLVM,RISCV,2075,"SrcReg = SDValue ( Result , <NUM_LIT> ) ;"
LLVM,RISCV,2076,"CurDAG -> setNodeMemRefs(cast <MachineSDNode>(Load), {"
LLVM,RISCV,2077,}
LLVM,RISCV,2078,VL = N;
LLVM,RISCV,2079,}
LLVM,RISCV,2080,
LLVM,RISCV,2081,
LLVM,RISCV,2082,
LLVM,RISCV,2083,"SplatVal = DAG.getTargetConstant(SplatImm, SDLoc(N), XLenVT);"
LLVM,RISCV,2084,if (SplatVal != nullptr) return true;
LLVM,RISCV,2085,"CurDAG->getNode(SplatVal, SDLoc(N), Subtarget->getXLenVT());"
LLVM,RISCV,2086,
LLVM,RISCV,2087,
LLVM,RISCV,2088,enter the case <STR_LIT> : statement and check for a specific condition.
LLVM,RISCV,2089,"SrcReg = SDValue(Result, <NUM_LIT> + 1);"
LLVM,RISCV,2090,
LLVM,RISCV,2091,
LLVM,RISCV,2092,
LLVM,RISCV,2093,IndexLMUL = TargetLowering::getLMUL(IndexVT);
LLVM,RISCV,2094,}
LLVM,RISCV,2095,CurDAG->setRoot(Store);
LLVM,RISCV,2096,
LLVM,RISCV,2097,
LLVM,RISCV,2098,if ( ! TSFlags || ! <STR_LIT> ( TSFlags ) ) return false ;
LLVM,RISCV,2099,
LLVM,RISCV,2100,default: return true;
LLVM,RISCV,2101,
LLVM,RISCV,2102,
LLVM,RISCV,2103,
LLVM,RISCV,2104,
LLVM,RISCV,2105,"Operands.push_back(CurDAG->getTargetConstant(Log2_32(Sew), DL, XLenVT));"
LLVM,RISCV,2106,
LLVM,RISCV,2107,
LLVM,RISCV,2108,
LLVM,RISCV,2109,if (Result != nullptr) {
LLVM,RISCV,2110,return true ;
LLVM,RISCV,2111,if (N.getOpcode() == <STR_LIT> && cast<VTSDNode>(N->getOperand(<NUM_LIT>))->getVT().bitsLE(<STR_LIT>)) {
LLVM,RISCV,2112,CurDAG -> RemoveModifiedNode ( Node ) ;
LLVM,RISCV,2113,}
LLVM,RISCV,2114,"SDValue MaskedLoad = CurDAG->getNode(ISD::VECTOR_LOAD, SDLoc(Node), P->getValueType(MaskedLoadTy), Operands);"
LLVM,RISCV,2115,Node->addOperand(StoreVal);
LLVM,RISCV,2116,
LLVM,RISCV,2117,"CurDAG->setNodeMemRefs(Store, {"
LLVM,RISCV,2118,IndexVT = getVT ( MVT::iPTR )
LLVM,RISCV,2119,
LLVM,RISCV,2120,
LLVM,RISCV,2121,LLVM_DEBUG(dbgs() << <STR_LIT> << Selected node:  << N->getMachineOpcode() << \n);
LLVM,RISCV,2122,
LLVM,RISCV,2123,return false ;
LLVM,RISCV,2124,
LLVM,RISCV,2125,}
LLVM,RISCV,2126,
LLVM,RISCV,2127,}
LLVM,RISCV,2128,CurDAG -> InsetNode(Result);
LLVM,RISCV,2129,case <STR_LIT>: {
LLVM,RISCV,2130,
LLVM,RISCV,2131,
LLVM,RISCV,2132,return true;
LLVM,RISCV,2133,return true;
LLVM,RISCV,2134,
LLVM,RISCV,2135,}
LLVM,RISCV,2136,
LLVM,RISCV,2137,SDValue ConstNode = cast < ConstantSDNode > (Node);
LLVM,RISCV,2138,return true ;
LLVM,RISCV,2139,
LLVM,RISCV,2140,
LLVM,RISCV,2141,return true;
LLVM,RISCV,2142,
LLVM,RISCV,2143,"ImmOperand = CurDAG -> getTargetConstant ( CombinedOffset , SDLoc ( ImmOperand ) , ImmOperand . getValueType ( ) ) ;"
LLVM,RISCV,2144,return;
LLVM,RISCV,2145,
LLVM,RISCV,2146,
LLVM,RISCV,2147,"SDValue VecOp = CurDAG->getNode(ISD::INSERT_SUBVECTOR, DL, MVT::getVectorVT(VT).getTypeForEVT(*DAG.getContext()), N, Lo, Hi, VL, CurDAG->getTargetConstant(SVE_VQ, DL, MVT::i32));"
LLVM,RISCV,2148,else {
LLVM,RISCV,2149,
LLVM,RISCV,2150,
LLVM,RISCV,2151,"getTargetFrameIndex(FIN->getIndex(), Subtarget->getXLenVT());"
LLVM,RISCV,2152,
LLVM,RISCV,2153,"additional code following this statement, as the return true;"
LLVM,RISCV,2154,}
LLVM,RISCV,2155,return true;
LLVM,RISCV,2156,
LLVM,RISCV,2157,}
LLVM,RISCV,2158,
LLVM,RISCV,2159,
LLVM,RISCV,2160,LLVM_DEBUG(dbgs() << Could not find constant or global address for combined offset << \n);
LLVM,RISCV,2161,LLVM_DEBUG (dbgs() << <STR_LIT>);
LLVM,RISCV,2162,
LLVM,RISCV,2163,
LLVM,RISCV,2164,SDValue Shl = N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ;
LLVM,RISCV,2165,
LLVM,RISCV,2166,assert ( N->getOperand(<NUM_LIT>)->isIntTy() );
LLVM,RISCV,2167,
LLVM,RISCV,2168,
LLVM,RISCV,2169,
LLVM,RISCV,2170,
LLVM,RISCV,2171,
LLVM,RISCV,2172,
LLVM,RISCV,2173,
LLVM,RISCV,2174,
LLVM,RISCV,2175,
LLVM,RISCV,2176,return true;
LLVM,RISCV,2177,
LLVM,RISCV,2178,std::cout << The value of SplatImm is not a valid unsigned integer.;
LLVM,RISCV,2179,
LLVM,RISCV,2180,"probably: <PRED_LIT> StoreNode = CurDAG -> getMachineNode ( <NUM_LIT> , SDLoc ( Node ) , Node -> getVTList ( ) , Operands ) ;"
LLVM,RISCV,2181,
LLVM,RISCV,2182,return Store;
LLVM,RISCV,2183,
LLVM,RISCV,2184,
LLVM,RISCV,2185,
LLVM,RISCV,2186,"<VAR_LIT> ReplaceNode ( Node , Store ) ;"
LLVM,RISCV,2187,case <STR_LIT>: or a default statement.
LLVM,RISCV,2188,}
LLVM,RISCV,2189,DEBUG(dbgs() << Instructions:)
LLVM,RISCV,2190,if ( Opcode == <STR_LIT> && VT == XLenVT ) {
LLVM,RISCV,2191,likely to involve the ending of a code block or a function with }
LLVM,RISCV,2192,
LLVM,RISCV,2193,
LLVM,RISCV,2194,}
LLVM,RISCV,2195,
LLVM,RISCV,2196,auto * ConstNode = cast < ConstantSDNode > ( Node ) ;
LLVM,RISCV,2197,if ( Bits < <NUM_LIT> ) return false ;
LLVM,RISCV,2198,
LLVM,RISCV,2199,
LLVM,RISCV,2200,"isConstantMask ( Op0 . getNode ( ) , Mask ), SDValue New= SDValue ( CurDAG -> getMachineNode ( <NUM_LIT> , SDLoc ( Node ) , MVT::uint32_t, Op0 , CurDAG -> getTargetConstant ( ShAmt, {"
LLVM,RISCV,2201,"ReplaceNode ( Node , CurDAG -> getMachineNode ( <STR_LIT> , DL , VT , Op0 , CurDAG -> getTargetConstant ( <NUM_LIT> , DL , VT ) , Op1 ) ) ;"
LLVM,RISCV,2202,return VL;
LLVM,RISCV,2203,VL = N;
LLVM,RISCV,2204,}
LLVM,RISCV,2205,
LLVM,RISCV,2206,return true;
LLVM,RISCV,2207,
LLVM,RISCV,2208,"CurDAG -> ReplaceAllUsesWith(Or.getNode(), Lower);"
LLVM,RISCV,2209,return RetTy;
LLVM,RISCV,2210,return ;
LLVM,RISCV,2211,return ;
LLVM,RISCV,2212,"SDValue NewShl = CurDAG->getNode(ISD::SHL, SDLoc(N), MVT::i32, Shl.getOperand(1), DAG.getTargetConstant(32, SDLoc(N), MVT::i32));"
LLVM,RISCV,2213,
LLVM,RISCV,2214,else if ( simm12 && ! signExtend ) Opcode = <STR_LIT> ;
LLVM,RISCV,2215,for (int i = 0;
LLVM,RISCV,2216,}
LLVM,RISCV,2217,++Position;
LLVM,RISCV,2218,
LLVM,RISCV,2219,return <ISA_LIT>FunctionPass ( );
LLVM,RISCV,2220,return NextInstruction();
LLVM,RISCV,2221,}
LLVM,RISCV,2222,Operands . push_back ( Chain ) ;
LLVM,RISCV,2223,
LLVM,RISCV,2224,"return createTupleImpl ( CurDAG , Regs , RegClassIDs [ NF - <NUM_LIT> ] , <STR_LIT> ) ;"
LLVM,RISCV,2225,
LLVM,RISCV,2226,"return createTupleImpl ( CurDAG , Regs , RegClassIDs [ NF - <NUM_LIT> ] , <STR_LIT>) ;"
LLVM,RISCV,2227,Result: Tuple object created with specified inputs.
LLVM,RISCV,2228,
LLVM,RISCV,2229,
LLVM,RISCV,2230,llvm_unreachable ( <STR_LIT> ) ;
LLVM,RISCV,2231,}
LLVM,RISCV,2232,return false;
LLVM,RISCV,2233,return true ;
LLVM,RISCV,2234,SDValue N01 = N0 . getOperand (1);
LLVM,RISCV,2235,
LLVM,RISCV,2236,MadeChange |= doPeepholeIMUL (N);
LLVM,RISCV,2237,
LLVM,RISCV,2238,virtual void atSelect ( void ) const override {
LLVM,RISCV,2239,return TargetMachine.run();
LLVM,RISCV,2240,
LLVM,RISCV,2241,return true;
LLVM,RISCV,2242,return true;
LLVM,RISCV,2243,
LLVM,RISCV,2244,
LLVM,RISCV,2245,C -> isUndef ( ) }
LLVM,RISCV,2246,return false;
LLVM,RISCV,2247,
LLVM,RISCV,2248,
LLVM,RISCV,2249,P->MemRefInfo = Node->getMemReferenceInfo();
LLVM,RISCV,2250,
LLVM,RISCV,2251,"<STR_LIT> return SDValue ( ReadVL , <NUM_LIT> ) ;"
LLVM,RISCV,2252,Node->op_begin() = Operands;
LLVM,RISCV,2253,}
LLVM,RISCV,2254,
LLVM,RISCV,2255,return nullptr;
LLVM,RISCV,2256,
LLVM,RISCV,2257,
LLVM,RISCV,2258,Ans: None
LLVM,RISCV,2259,
LLVM,RISCV,2260,SplatValue = SplatImm;
LLVM,RISCV,2261,"SplatImm = SignExtend64(SplatImm, EltVT.getSizeInBits());"
LLVM,RISCV,2262,
LLVM,RISCV,2263,return false;
LLVM,RISCV,2264,If ( Args.size() > <NUM_LIT>) {
LLVM,RISCV,2265,Output: End of code snippet.
LLVM,RISCV,2266,return VT;
LLVM,RISCV,2267,
LLVM,RISCV,2268,
LLVM,RISCV,2269,Return RVLocs;
LLVM,RISCV,2270,
LLVM,RISCV,2271,assert(VA.getLocInfo() == CCValAssign::Full);
LLVM,RISCV,2271,
LLVM,RISCV,2272,return Value;
LLVM,RISCV,2273,"default: return DAG.getNode(ISD::UNDEF, DL, VA.getLocVT());"
LLVM,RISCV,2274,
LLVM,RISCV,2275,"return emitCALL ( MI , MBB ) ;"
LLVM,RISCV,2276,
LLVM,RISCV,2277,SDValue DV = Op . getOperand (0);
LLVM,RISCV,2278,case 'N' :
LLVM,RISCV,2279,else return STR_LIT;
LLVM,RISCV,2280,return <INT_LIT>;
LLVM,RISCV,2281,
LLVM,RISCV,2282,"return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ;"
LLVM,RISCV,2283,
LLVM,RISCV,2284,"if (ConstantPoolSDNode *N = dyn_cast<ConstantPoolSDNode>(Op)) return DAG.getTargetConstantPool(N->getMachineFunction(), Ty, N->getConstVal(), N->getAlign(), N->getTargetFlags());"
LLVM,RISCV,2285,OPCODE ( RETURN ) ;
LLVM,RISCV,2286,TargetMachine::getAsmTargetFixupKindInfo(.Definition.Expansion)
LLVM,RISCV,2287,}
LLVM,RISCV,2288,}
LLVM,RISCV,2289,if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) {
LLVM,RISCV,2290,
LLVM,RISCV,2291,
LLVM,RISCV,2292,return Result;
LLVM,RISCV,2293,"else Result = DAG.getTargetGlobalAddress(CP->getGlobalValue(), PtrVT, CP->getOffset(), 0, 0);"
LLVM,RISCV,2294,"ArgValue = DAG . getNode ( ISD :: <STR_LIT> , DL , <STR_LIT> , ArgValue ) ;"
LLVM,RISCV,2295,"SDValue FrameAddr = DAG.getNode(ISD::FRAMEADDR, DL, getPointerTy(DAG.getDataLayout()), DAG.getIntPtrConstant(FrameIndex, DL));"
LLVM,RISCV,2296,}
LLVM,RISCV,2297,
LLVM,RISCV,2298,
LLVM,RISCV,2299,"SDValue Lo = DAG.addNode(<NUM_LIT>, DL, PtrVT, TGALo);"
LLVM,RISCV,2300,
LLVM,RISCV,2301,"case <STR_LIT> : return lowerExternalSymbol ( cast < ExternalSymbolSDNode > ( Op ) , DAG ) ;"
LLVM,RISCV,2302,
LLVM,RISCV,2303,SDValue FrameIndex = FunctionArguments[ Arg ].get<NUM_LIT>();
LLVM,RISCV,2304,
LLVM,RISCV,2305,
LLVM,RISCV,2306,"return DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, DAG.getConstant(1, MVT::i32), DAG.getConstant(0, MVT::i32)) ;"
LLVM,RISCV,2307,
LLVM,RISCV,2308,"return DAG.getNode(ISA_LIT::STACKSAVE, SDLoc(Op), MVT::i64, DAG.getRegister(Mips::SP, MVT::i64));"
LLVM,RISCV,2309,
LLVM,RISCV,2310,
LLVM,RISCV,2311,EVT ValVT = Op.getValueType();
LLVM,RISCV,2312,
LLVM,RISCV,2313,else if (Ins[i+1].isOrigArg()) ArgTy = FType->getParamType(Ins[i+1].getOrigArgIndex());
LLVM,RISCV,2314,
LLVM,RISCV,2315,
LLVM,RISCV,2316,return BAHi;
LLVM,RISCV,2317,
LLVM,RISCV,2318,
LLVM,RISCV,2319,return Op.getOperand(0).getZExtValue();
LLVM,RISCV,2320,
LLVM,RISCV,2321,return GAHi;
LLVM,RISCV,2322,
LLVM,RISCV,2323,
LLVM,RISCV,2324,
LLVM,RISCV,2325,
LLVM,RISCV,2326,
LLVM,RISCV,2327,"Val = DAG.getNode(<STR_LIT>, DL, LocVT, Val);"
LLVM,RISCV,2328,"setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ;"
LLVM,RISCV,2329,"Val = DAG.getNode(<STR_LIT>, DL, ValVT, Val);"
LLVM,RISCV,2330,"Val = BuildSDNode ( VA . getOpcode ( ) , SDLoc ( Op ) , LocVT , ValVT ) ;"
LLVM,RISCV,2331,ABI = MF.getRegInfo().getABI();
LLVM,RISCV,2332,}
LLVM,RISCV,2333,return true;
LLVM,RISCV,2334,
LLVM,RISCV,2335,if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) {
LLVM,RISCV,2336,
LLVM,RISCV,2337,case <STR_LIT> : return 1 ;
LLVM,RISCV,2338,}
LLVM,RISCV,2339,case CCValAssign :: Indirect :
LLVM,RISCV,2340,"SDValue NewOp2 = DAG.getNode(<STR_LIT>, DL, <STR_LIT>, N->getOperand(<NUM_LIT>)->getNextNode());"
LLVM,RISCV,2341,"NewOp2 = DAG.getNode(ADD, DL, i32, N->getOperand(2));"
LLVM,RISCV,2342,
LLVM,RISCV,2343,
LLVM,RISCV,2344,}
LLVM,RISCV,2345,}
LLVM,RISCV,2346,->getFallThrough();
LLVM,RISCV,2347,
LLVM,RISCV,2348,
LLVM,RISCV,2349,
LLVM,RISCV,2350,if (PersonalityFn == nullptr) {
LLVM,RISCV,2351,
LLVM,RISCV,2352,
LLVM,RISCV,2353,"a default case, which handles all other possible cases that are not explicitly listed. It could also be the end of the switch statement, closing the curly brackets }"
LLVM,RISCV,2354,Info.memPtr = PtrTy->getPointer ( );
LLVM,RISCV,2355,
LLVM,RISCV,2356,if (C1Cost < 0) C1Cost = -C1Cost;
LLVM,RISCV,2357,}
LLVM,RISCV,2358,
LLVM,RISCV,2359,"Addr = getDynamicTLSAddr(N, DAG);"
LLVM,RISCV,2360,"RetOps . push_back ( DAG . getRegister ( RegHi , <STR_LIT> ) ) ;"
LLVM,RISCV,2361,
LLVM,RISCV,2362,assert (N->getValueType(<NUM_LIT>) == <STR_LIT> && Subtarget.is64Bit() && Subtarget.hasStdExtM() && <STR_LIT>);
LLVM,RISCV,2363,Val = FIN.getPointer();
LLVM,RISCV,2364,"check the location information of the given value VA. If it is set to CCValAssign::Indirect, the code"
LLVM,RISCV,2365,
LLVM,RISCV,2366,return STI . isO16 ( Reg ) ;
LLVM,RISCV,2367,"<ISA_LIT>InvalidCCReservedRegs , reserved registers must not be used as arguments }"
LLVM,RISCV,2368,"State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , StackOffset , LocVT , LocInfo ) ) ;"
LLVM,RISCV,2369,}
LLVM,RISCV,2370,
LLVM,RISCV,2371,RVFI -> setVarArgsGPRIndex ( RegInfo . createVirtualRegister ( RC ) ) ;
LLVM,RISCV,2372,if (GV == nullptr) {
LLVM,RISCV,2373,"RetOps . push_back ( DAG . getRegister ( RegHi , <STR_LIT> ) ) ;"
LLVM,RISCV,2374,
LLVM,RISCV,2375,The code snippet ends with the statement return true;
LLVM,RISCV,2376,
LLVM,RISCV,2377,int LoIdx = DstRC -> getSubReg < <NUM_LIT> > ( HiReg ) ;
LLVM,RISCV,2378,
LLVM,RISCV,2379,
LLVM,RISCV,2380,else return true ;
LLVM,RISCV,2381,if ( VT == <STR_LIT> ) return true ;
LLVM,RISCV,2382,case ISD::INTRINSIC_WO_CHAIN: default: return Op;
LLVM,RISCV,2383,if (IntNo == <NUM_LIT>) {
LLVM,RISCV,2384,"return DAG.getNode(<STR_LIT>, DL, <STR_LIT>, FPConv);"
LLVM,RISCV,2385,assert (N -> getValueType(<NUM_LIT>) == <STR_LIT> && Subtarget.is64Bit() && Subtarget.hasStdExtF() && <STR_LIT>) ;
LLVM,RISCV,2386,if ( Arg . Flags . isByVal ( ) ) return false ;
LLVM,RISCV,2387,
LLVM,RISCV,2388,"if (Offset != 0) return DAG.getNode(add, DL, Ty, Addr, DAG.getConstant(Offset, DL, XLenVT));"
LLVM,RISCV,2389,
LLVM,RISCV,2390,if ( Reg ) {
LLVM,RISCV,2391,
LLVM,RISCV,2392,}
LLVM,RISCV,2393,if (C1Cost < ShiftedC1Cost) return true;
LLVM,RISCV,2394,if ( ! <NUM_LIT> ) return false ;
LLVM,RISCV,2395,
LLVM,RISCV,2396,Results . push_back ( FPConv ) ;
LLVM,RISCV,2397,case <STR_LIT> : doSomething(VReg) ;
LLVM,RISCV,2398,
LLVM,RISCV,2399,"If the statement unsigned StackOffset = Reg ? <NUM_LIT> : State . AllocateStack ( XLen / <NUM_LIT> , XLen / <NUM_LIT> ) ;"
LLVM,RISCV,2400,return false ;
LLVM,RISCV,2401,
LLVM,RISCV,2402,"F->insert(I, IfFalseMBB);"
LLVM,RISCV,2403,default: return null;
LLVM,RISCV,2404,
LLVM,RISCV,2405,RegInfo . <ISA_LIT>RegisterLiveIn (<REG_NUM_LIT>) ;
LLVM,RISCV,2406,"RetOps.push_back(DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), VA.getLocVT(), Flag));"
LLVM,RISCV,2407,if (VA.isRegLoc()) {
LLVM,RISCV,2408,
LLVM,RISCV,2409,Default case:
LLVM,RISCV,2410,
LLVM,RISCV,2411,
LLVM,RISCV,2412,}
LLVM,RISCV,2413,
LLVM,RISCV,2414,}
LLVM,RISCV,2415,"return false. If the split has ended and the size of PendingLocs is less than or equal to <NUM_LIT>, the function"
LLVM,RISCV,2416,
LLVM,RISCV,2417,"return TargetLowering :: getRegisterTypeForCallingConv ( Context , CC , VT ) ;"
LLVM,RISCV,2418,
LLVM,RISCV,2419,}
LLVM,RISCV,2420,
LLVM,RISCV,2421,}
LLVM,RISCV,2422,return Subtarget.hasVInstructionsF64();
LLVM,RISCV,2423,if (ScalarTy -> isDoubleTy()) return Subtarget.hasVInstructionsF64();
LLVM,RISCV,2424,"return DAG.getNode(<STR_LIT>, DL, VT, DAG.getConstant(Adjust, DL, VT), Trunc);"
LLVM,RISCV,2425,"SDValue Neg = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , DL , VT ) , Src ) ;"
LLVM,RISCV,2426,"SDValue TableNode = DAG.getConstant(Table, DL, XLenVT);"
LLVM,RISCV,2427,"something like SDValue MADD = DAG.getNode(<STR_LIT>, DL, VTs, RM, Chain);"
LLVM,RISCV,2428,
LLVM,RISCV,2429,"SDValue And = DAG.getNode(Opcode, DL, XLenVT, SysRegNo, Shift);"
LLVM,RISCV,2430,SDValue RMValue = Op -> getOperand ( <NUM_LIT> ) ;
LLVM,RISCV,2431,
LLVM,RISCV,2432,
LLVM,RISCV,2433,
LLVM,RISCV,2434,if ( LMul > Subtarget . getMaxLMULForFixedLengthVectors ( ) ) return false ;
LLVM,RISCV,2435,The next statement could potentially be either another case statement checking for a specific instruction type (i.e. case <STR_LIT>:) or a return statement.
LLVM,RISCV,2436,"RetOps . push_back ( DAG . getRegister ( RegHi , <STR_LIT> ) ) ;"
LLVM,RISCV,2437,if ( RC == & <STR_LIT> ) return State . AllocateReg ( ArgVRM2s ) ;
LLVM,RISCV,2438,Optional<unsigned> SecondMaskArgument;
LLVM,RISCV,2439,
LLVM,RISCV,2440,"a conditional statement beginning with if that calls the function Fn and passes in the arguments MF.getDataLayout(), ABI, i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo, Outs[i].IsFixed, IsRet, OrigTy, *this, and FirstMaskArgument."
LLVM,RISCV,2441,
LLVM,RISCV,2442,}
LLVM,RISCV,2443,}
LLVM,RISCV,2444,a closing }
LLVM,RISCV,2445,}
LLVM,RISCV,2446,return false;
LLVM,RISCV,2447,}
LLVM,RISCV,2448,
LLVM,RISCV,2449,
LLVM,RISCV,2450,Mask = <STR_LIT> ( EltBits ) ;
LLVM,RISCV,2451,"Op0 = DAG.getNode(ExtOpc, DL, VT, Op0, Op1);"
LLVM,RISCV,2452,"return DAG . getNode ( <STR_LIT> , DL , VT , LHS -> Op , RHS -> Op ) ;"
LLVM,RISCV,2453,> matchGREVIPat ( Op . getOperand ( <NUM_LIT> ) ) && LHS->formsPairWith ( * RHS ) ) {
LLVM,RISCV,2454,}
LLVM,RISCV,2455,"SDValue N2 = DAG.getNode(ISD::XOR, SDLoc(N), N->getValueType(0), N0, N1);"
LLVM,RISCV,2456,return Result;
LLVM,RISCV,2457,if ( ShAmt & <NUM_LIT> ) x = ( ( x & <NUM_LIT> ) << <NUM_LIT> ) | ( ( x & <NUM_LIT> ) >> <NUM_LIT> ) ;
LLVM,RISCV,2458,
LLVM,RISCV,2459,Known . Zero . reverseBits ( ) ;
LLVM,RISCV,2460,return Subtarget.getXLen() - Op.getOperand(<NUM_LIT>).getScalarValueSizeInBits() + <NUM_LIT>;
LLVM,RISCV,2461,
LLVM,RISCV,2462,"Val = DAG.getNode(<STR_LIT>, DL, VA.getValVT(), Val);"
LLVM,RISCV,2463,
LLVM,RISCV,2464,`}
LLVM,RISCV,2465,"return DAG.getNode(<STR_LIT>, DL, VT, DAG.getUNDEF(VT), V, <STR_LIT>);"
LLVM,RISCV,2466,assert (V.getValueType().getNumElements() == VT.getNumElements() && <STR_LIT>) ;
LLVM,RISCV,2467,{
LLVM,RISCV,2468,
LLVM,RISCV,2469,
LLVM,RISCV,2470,NewWOp.setDebugLoc(DL);
LLVM,RISCV,2471,SDNode *NewNode = dyn_cast<SDNode*>(NewWOp);
LLVM,RISCV,2472,
LLVM,RISCV,2473,
LLVM,RISCV,2474,
LLVM,RISCV,2475,
LLVM,RISCV,2476,
LLVM,RISCV,2477,
LLVM,RISCV,2478,"Value * Result = Builder . CreateCall ( MaskedCmpXchg , {"
LLVM,RISCV,2479,ic_cast <uint64_t>(Ord)) ;
LLVM,RISCV,2480,"BuildMI ( DoneMBB , DL , TII -> get ( <STR_LIT> ) , ReadAgainReg ) . addImm ( <STR_LIT> ( <STR_LIT> ) -> Encoding ) . addReg ( <STR_LIT> ) ;"
LLVM,RISCV,2481,RegInfo.addLiveIn(ReadAgainReg);
LLVM,RISCV,2482,"TailMBB -> insert ( InsertionPoint , SelectMBBI -> removeFromParent ( ) ) ;"
LLVM,RISCV,2483,
LLVM,RISCV,2484,"TII.loadRegFromStackSlot(MBB, II, LoReg, FI, SrcRC, RI);"
LLVM,RISCV,2485,
LLVM,RISCV,2486,
LLVM,RISCV,2487,"return DAG.getBitcast(VT, L);"
LLVM,RISCV,2488,
LLVM,RISCV,2489,"StoredVal = DAG.getNode(ISD::BITCAST, DL, NewVT, StoredVal);"
LLVM,RISCV,2490,}
LLVM,RISCV,2491,
LLVM,RISCV,2492,
LLVM,RISCV,2493,
LLVM,RISCV,2494,MVT DoubleXLen = Subtarget.getDoubleXLenVT();
LLVM,RISCV,2495,TargetLowering::CLI.AnalyzeCallResult();
LLVM,RISCV,2496,
LLVM,RISCV,2497,
LLVM,RISCV,2498,
LLVM,RISCV,2499,a closing brace (}
LLVM,RISCV,2500,return true;
LLVM,RISCV,2501,
LLVM,RISCV,2502,
LLVM,RISCV,2503,case <NUM_LIT> : a break statement or another case statement followed by a break. This is assuming there are multiple cases within the switch statement.
LLVM,RISCV,2504,return <STR_LIT> :: LMUL_8 ;
LLVM,RISCV,2505,
LLVM,RISCV,2506,
LLVM,RISCV,2507,
LLVM,RISCV,2508,return <REG_CLS_ID>;
LLVM,RISCV,2509,
LLVM,RISCV,2510,if ( Reg == <STR_LIT> ) {
LLVM,RISCV,2511,
LLVM,RISCV,2512,"an if-else statement with CC being compared to CallingConv::C and the return statements being EVT or MVT::i64 depending on the result. Alternatively, it could be a switch statement with different cases for different values of CC and the corresponding return statements."
LLVM,RISCV,2513,return MVT :: <STR_LIT> ;
LLVM,RISCV,2514,"return DAG.getNode(ISD::SETCC, DL, MVT::i1, DAG.getConstant(ISD::SETLE, DL, MVT::i32), Mask, VL);"
LLVM,RISCV,2515,}
LLVM,RISCV,2516,else return VT.changeVectorElementTypeToInteger();
LLVM,RISCV,2517,"SDValue MNAdd = SDValue (DAG.getMachineNode(<STR_LIT>, DL, Ty, AddrAdd), <NUM_LIT>) ;"
LLVM,RISCV,2518,"SDValue MNAdd = SDValue(DAG.getMachineNode(<STR_LIT>, DL, Ty, AddrAdd), <NUM_LIT>);"
LLVM,RISCV,2519,return <STR_LIT> ;
LLVM,RISCV,2520,"return DAG.getTargetJumpTable(N, Ty, Flags);"
LLVM,RISCV,2521,
LLVM,RISCV,2522,
LLVM,RISCV,2523,
LLVM,RISCV,2524,
LLVM,RISCV,2525,
LLVM,RISCV,2526,
LLVM,RISCV,2527,
LLVM,RISCV,2528,}
LLVM,RISCV,2529,
LLVM,RISCV,2530,
LLVM,RISCV,2531,<STR_LIT> : return Subtarget . hasStdExtDx ( ) ;
LLVM,RISCV,2532,if ( VT == <STR_LIT> && ! Subtarget . hasStdExtD ( ) ) return false;
LLVM,RISCV,2533,if ( ScalarTy -> isStructTy ( ) ) return Subtarget . hasStdExtU ( ) ;
LLVM,RISCV,2534,return false;
LLVM,RISCV,2535,else return false;
LLVM,RISCV,2536,
LLVM,RISCV,2537,if (SeqAddend == Addend) {
LLVM,RISCV,2538,}
LLVM,RISCV,2539,
LLVM,RISCV,2540,
LLVM,RISCV,2541,std::cout << N->getAddressSpace() << std::endl;
LLVM,RISCV,2542,N->getBlock();
LLVM,RISCV,2543,
LLVM,RISCV,2544,"return DAG . getBitcast ( Op . getValueType ( ) , Slidedown ) ;"
LLVM,RISCV,2545,}
LLVM,RISCV,2546,"return convertFromScalableVector(ExtVT, Ext, DAG, Subtarget);"
LLVM,RISCV,2547,"return scalarizeVectorOp(Op, DL, ExtVT, ContainerVT, Op1);"
LLVM,RISCV,2548,
LLVM,RISCV,2549,return Result ;
LLVM,RISCV,2550,"else if ( VT . getVectorElementType ( ) == <I32> ) return lowerToScalableOp ( Op , DAG , MaskOpc , true ) ;"
LLVM,RISCV,2551,"SDValue Result = DAG.getNode(<STR_LIT>, DL, ContainerVT, Select, Mask);"
LLVM,RISCV,2552,"SDValue Result = DAG.getNode(ISD::ADD, DL, Op1, Op2);"
LLVM,RISCV,2553,
LLVM,RISCV,2554,}
LLVM,RISCV,2555,
LLVM,RISCV,2556,else {
LLVM,RISCV,2557,PartOffset += Offset ;
LLVM,RISCV,2558,
LLVM,RISCV,2559,SDNode *FpToInt = cast<SDNode>(FpToInt) ? FpToInt : ZeroInt;
LLVM,RISCV,2560,
LLVM,RISCV,2561,"static const SDValue Mask = DAG.getNode(ISD::AND, DL, MVT::i32, Shift, DAG.getConstant(<NUM_LIT> - <NUM_LIT>, DL, MVT::i32));"
LLVM,RISCV,2562,
LLVM,RISCV,2563,if (Offset == <NUM_LIT>) {
LLVM,RISCV,2564,}
LLVM,RISCV,2565,
LLVM,RISCV,2566,
LLVM,RISCV,2567,"return lowerVectorIntrinsicSplats(Op, DAG, Subtarget);"
LLVM,RISCV,2568,return DAG.getMergeValues({
LLVM,RISCV,2569,"return getJumpTableAddr(N, DAG);"
LLVM,RISCV,2570,
LLVM,RISCV,2571,
LLVM,RISCV,2572,if ( VT .isFixedLengthVector ( ) ) {
LLVM,RISCV,2573,assert(! IsTruncatingStore && <STR_LIT>) ;
LLVM,RISCV,2574,assert ( Mask . getValueType ( ) == MaskVT && <STR_LIT> ) ;
LLVM,RISCV,2575,
LLVM,RISCV,2576,unsigned MaskID = IsUnmasked ? <STR_LIT> : <STR_LIT> ;
LLVM,RISCV,2577,
LLVM,RISCV,2578,{
LLVM,RISCV,2579,
LLVM,RISCV,2580,if (VT == XLenVT && CondV.getOpcode() == G_FCMP && CondV.getOperand(1).getSimpleValueType() == XLenVT) {
LLVM,RISCV,2581,
LLVM,RISCV,2582,"SDValue MVValue = DAG.getNode(<STR_LIT>, DL, XLenVT, RMValue, Op);"
LLVM,RISCV,2583,"SDValue Offset = DAG.getNode(<STR_LIT>, DL, XLenVT, RMValue, DAG.getConstant(<NUM_LIT>, DL, XLenVT));"
LLVM,RISCV,2584,
LLVM,RISCV,2585,"SDValue XLenMinus2 = DAG . getConstant ( Subtarget . getXLen ( ) - 2 , DL , VT ) ;"
LLVM,RISCV,2586,
LLVM,RISCV,2587,"CC = DAG.getSetCC(DL, VT, MinusXLen, ShiftRightLo, HiTrue) ;"
LLVM,RISCV,2588,"SDValue Vec = DAG.getNode(ISD::AND, DL, VT, Op, Mask, VL)"
LLVM,RISCV,2589,
LLVM,RISCV,2590,"SDValue ScalableVL = DAG.getNode(ScalableOpc, DL, VT, Ops, Mask, VL);"
LLVM,RISCV,2591,return ScalableRes;
LLVM,RISCV,2592,
LLVM,RISCV,2593,
LLVM,RISCV,2594,"return DAG.getNode(<STR_LIT>, DL, VecVT, Src, SplatTrueVal, SplatZero, CC, Mask, VL);"
LLVM,RISCV,2595,}
LLVM,RISCV,2596,:
LLVM,RISCV,2597,
LLVM,RISCV,2598,"SplatOne = DAG.getNode( trunc, DL, VecVT, Src, SplatOne) ;"
LLVM,RISCV,2599,"Vec = DAG . getNode ( ADD , DL , XLenVT , Zero , Vec , TrueMask , VL ) ;"
LLVM,RISCV,2600,
LLVM,RISCV,2601,
LLVM,RISCV,2602,}
LLVM,RISCV,2603,
LLVM,RISCV,2604,}
LLVM,RISCV,2605,"SDValue MaskedOp = DAG.getNode(ShlExpMask ? ISD::SHL : ISD::SRL, DL, VT, Src, DAG.getConstant(ShAmt, DL, WidthVT));"
LLVM,RISCV,2606,{
LLVM,RISCV,2607,return None;
LLVM,RISCV,2608,
LLVM,RISCV,2609,
LLVM,RISCV,2610,else return nullptr;
LLVM,RISCV,2611,"if ( SDValue V = transformAddShlImm ( N , DAG, Subtarget ) ) return combineSelectAndUseCommutative ( N , DAG , false );"
LLVM,RISCV,2612,
LLVM,RISCV,2613,
LLVM,RISCV,2614,
LLVM,RISCV,2615,
LLVM,RISCV,2616,
LLVM,RISCV,2617,
LLVM,RISCV,2618,
LLVM,RISCV,2619,
LLVM,RISCV,2620,
LLVM,RISCV,2621,}
LLVM,RISCV,2622,
LLVM,RISCV,2623,}
LLVM,RISCV,2624,}
LLVM,RISCV,2625,
LLVM,RISCV,2626,
LLVM,RISCV,2627,
LLVM,RISCV,2628,return false;
LLVM,RISCV,2629,"Sinker (Insn, U.getIndex()))) {"
LLVM,RISCV,2630,}
LLVM,RISCV,2631,
LLVM,RISCV,2632,"Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Scalar , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ;"
LLVM,RISCV,2633,Return false;
LLVM,RISCV,2634,if ( ISD :: isNormalShl ( Op . <Already visited> ) == <NUM_LIT> ) return false
LLVM,RISCV,2635,if ( NewMask == ExpandedMask) return true;
LLVM,RISCV,2636,"return DAG.getNode(<STR_LIT>, DL, VT, New1, DAG.getConstant(C1, DL, VT));"
LLVM,RISCV,2637,"SDValue result_node = DAG.getNode(<NUM_LIT>, DL, VT, NA1, DAG.getConstant(<NUM_LIT>, DL, VT));"
LLVM,RISCV,2638,
LLVM,RISCV,2639,
LLVM,RISCV,2640,
LLVM,RISCV,2641,if (LocVT.isSimple()) {
LLVM,RISCV,2642,return !Subtarget . useRVV ();
LLVM,RISCV,2643,
LLVM,RISCV,2644,}
LLVM,RISCV,2645,}
LLVM,RISCV,2646,if (Idx == 0) continue;
LLVM,RISCV,2647,Created . push_back ( Add . getNode ( ) ) ;
LLVM,RISCV,2648,return SDValue();
LLVM,RISCV,2649,
LLVM,RISCV,2650,
LLVM,RISCV,2651,
LLVM,RISCV,2652,
LLVM,RISCV,2653,"return emitQuietFCMP ( MI , BB , <STR_LIT> , <STR_LIT> , Subtarget );"
LLVM,RISCV,2654,"BuildMI(*BB, MI, DL, TII.get(<STR_LIT>));"
LLVM,RISCV,2655,return X86ISD :: RJUMP32 ;
LLVM,RISCV,2656,return <STR_LIT> ;
LLVM,RISCV,2657,break;
LLVM,RISCV,2658,return true;
LLVM,RISCV,2659,
LLVM,RISCV,2660,return false;
LLVM,RISCV,2661,"return isOperationLegal ( < > , VT ) ;"
LLVM,RISCV,2662,
LLVM,RISCV,2663,if ( Elt == i / <NUM_LIT> ) return false ;
LLVM,RISCV,2664,EVT MemVT = LD - > getMemoryVT ( ) ;
LLVM,RISCV,2665,return Val;
LLVM,RISCV,2666,}
LLVM,RISCV,2667,
LLVM,RISCV,2668,MVT VecVT = Vec.getSimpleValueType();
LLVM,RISCV,2669,"SDValue Result = DAG.getNode(RVVOpcode, DL, VecEltVT, VectorVal, Mask, VL, ScalarSplat);"
LLVM,RISCV,2670,Scalar VT Mask = VL = VectorVal;
LLVM,RISCV,2671,return FpToInt;
LLVM,RISCV,2672,"MaxValNode = DAG . getMaxVal ( VT , DL , Precision ) ;"
LLVM,RISCV,2673,
LLVM,RISCV,2674,Ops.push_back(Load->getBasePtr());
LLVM,RISCV,2675,}
LLVM,RISCV,2676,"DAG.getNode(ISD::FADD, DL, MVT::v2f32, Op1, Op2)"
LLVM,RISCV,2677,"return DAG.getSelect(DL, VT, Val, ContainerVT);"
LLVM,RISCV,2678,
LLVM,RISCV,2679,
LLVM,RISCV,2680,"SDValue Res = DAG.getNode(ISD::GATHER, DL, VT, Ops);"
LLVM,RISCV,2681,
LLVM,RISCV,2682,SDValue VecEltVT = getScalarType(VecVT);
LLVM,RISCV,2683,"return DAG.getSExtOrTrunc(Elt0, DL, Op.getValueType());"
LLVM,RISCV,2684,
LLVM,RISCV,2685,"return DAG.getSExtOrTrunc(Elt0, DL, Op.getValueType());"
LLVM,RISCV,2686,"SDValue Result = DAG.getNode(RVVOpcode, DL, VecEltVT, Vec, VL, Mask, M1VT, XLenVT);"
LLVM,RISCV,2687,
LLVM,RISCV,2688,if ( CheckUndefs ( Shift ) && MatchShift ( Shift ) ) return Shift ;
LLVM,RISCV,2689,
LLVM,RISCV,2690,"SDValue FPToIntZero = DAG.getNode(Opc, DL, DstVT, FpToInt, ZeroInt);"
LLVM,RISCV,2691,return SDValue();
LLVM,RISCV,2692,
LLVM,RISCV,2693,return true;
LLVM,RISCV,2694,
LLVM,RISCV,2695,"APInt NumElements = APInt::getNullValue(Context, ValueVTBitSize / PartVTBitSize);"
LLVM,RISCV,2696,"Op1 = DAG.getNode(WMulOpc, DL, VT, Op0, Op1);"
LLVM,RISCV,2697,
LLVM,RISCV,2698,if ( Addend != * SeqAddend ) return None;
LLVM,RISCV,2699,if (AI->getOperation() == AtomicRMWInst::Min || AI->getOperation() == AtomicRMWInst::Max)
LLVM,RISCV,2700,return <STR_LIT> ;
LLVM,RISCV,2701,return <STR_LIT> ;
LLVM,RISCV,2702,Info . size = NULL;
LLVM,RISCV,2703,"setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ;"
LLVM,RISCV,2704,
LLVM,RISCV,2705,if ( Size == <NUM_LIT> || Size == <NUM_LIT> ) return AtomicExpansionKind :: MaskedIntrinsic ;
LLVM,RISCV,2706,return <STR_LIT> ;
LLVM,RISCV,2707,
LLVM,RISCV,2708,break ;
LLVM,RISCV,2709,
LLVM,RISCV,2710,
LLVM,RISCV,2711,
LLVM,RISCV,2712,
LLVM,RISCV,2713,
LLVM,RISCV,2714,"auto *AtomicFence = Builder.CreateAtomicCmpXchg(AlignedAddr, CmpVal, NewVal, Mask, Ordering, Ordering);"
LLVM,RISCV,2715,
LLVM,RISCV,2716,"setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ;"
LLVM,RISCV,2717,"StackOffset = Align ( StackOffset , StackAlign ) ;"
LLVM,RISCV,2718,}
LLVM,RISCV,2719,
LLVM,RISCV,2720,
LLVM,RISCV,2721,}
LLVM,RISCV,2722,case <STR_LIT> : {
LLVM,RISCV,2723,CCValAssign VA = PendingLocs[1];
LLVM,RISCV,2724,
LLVM,RISCV,2725,
LLVM,RISCV,2726,"setOperationAction ( <STR_LIT> , XLenVT , Expand ) ;"
LLVM,RISCV,2727,
LLVM,RISCV,2728,"DAG.getNode(STR_LIT, DL, VecEltVT, Reduction, DAG.getConstant(<NUM_LIT>, DL, Subtarget.getXLenVT()));"
LLVM,RISCV,2729,"return DAG . getNode ( <STR_LIT> , DL , VecEltVT , Reduction , DAG . getConstant ( <NUM_LIT> , DL , Subtarget . getXLenVT ( ) ) ) ;"
LLVM,RISCV,2730,"return lowerVectorIntrinsicShuffles(Op, DAG, Subtarget);"
LLVM,RISCV,2731,return DAG . getMergeValues ( {
LLVM,RISCV,2732,}
LLVM,RISCV,2733,"VL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ContainerVT, PassThru, Mask) ;"
LLVM,RISCV,2734,"MaskVT = convertToScalableVector ( MaskVT , Mask , DAG , Subtarget ) ;"
LLVM,RISCV,2735,"if (IsUnmasked) SDValue ST = DAG.getTruncStore(MSN->getChain(), DL, Val, Index, Mask, XLenVT, VL);"
LLVM,RISCV,2736,"IntID = DAG.getRegister(<STR_LIT>, XLenVT);"
LLVM,RISCV,2737,SDValue Mask_VL = Op.getOperand(<NUM_LIT>);
LLVM,RISCV,2738,if (VecEVT.isSimple() && VecEVT < Desc->getValueType(0)) {
LLVM,RISCV,2739,"return DAG.getSExtOrTrunc(Elt0, DL, Op.getValueType());"
LLVM,RISCV,2740,"return DAG . getSetCC ( DL , XLenVT , Vec , One , <STR_LIT> ) ;"
LLVM,RISCV,2741,}
LLVM,RISCV,2742,}
LLVM,RISCV,2743,
LLVM,RISCV,2744,
LLVM,RISCV,2745,
LLVM,RISCV,2746,
LLVM,RISCV,2747,if(VecVT == MVT::i32) {
LLVM,RISCV,2748,
LLVM,RISCV,2749,case MVT::v16i8:.
LLVM,RISCV,2750,"SDValue One = DAG.getNode(ISD::SPLAT_VECTOR, DL, ContainerVT, Mask);"
LLVM,RISCV,2751,
LLVM,RISCV,2752,
LLVM,RISCV,2753,
LLVM,RISCV,2754,
LLVM,RISCV,2755,return true;
LLVM,RISCV,2756,"return DAG .getNode (, DL, ContainerVT, Vec, ExtractElementIdx);"
LLVM,RISCV,2757,"SDValue Select = DAG.getNode(<STR_LIT>, DL, VT, Cmp, Op1, Op2);"
LLVM,RISCV,2758,
LLVM,RISCV,2756,"return DAG . getNode ( <STR_LIT> , DL , EltVT , Vec , Idx ) ;"
LLVM,RISCV,2757,"SDValue Result = DAG.getNode(SD, DL, ResultVT, Cmp);"
LLVM,RISCV,2758,
LLVM,RISCV,2759,
LLVM,RISCV,2760,case TLSModel :: LocalDynamic : <NUM_LIT> default switch statement }
LLVM,RISCV,2761,
LLVM,RISCV,2762,
LLVM,RISCV,2763,
LLVM,RISCV,2764,"<STR_LIT> = convertToMask ( MaskVT , Mask , DAG , Subtarget ) ;"
LLVM,RISCV,2765,"SDValue Result = DAG.getNode(Opcode, DL, VT, Ops);"
LLVM,RISCV,2766,"SDValue Store = DAG.getNode(ISD::STORE, DL, MVT::Other, Val, BasePtr, Index, NULL, MachinePointerInfo(), 0, false, wasMemIndexed, isTruncatingStore, VL.getOperand(1));"
LLVM,RISCV,2767,
LLVM,RISCV,2768,
LLVM,RISCV,2769,
LLVM,RISCV,2770,"SDValue SplatNegOne = DAG.getConstant(<NUM_LIT>, DL, Subtarget.getXLenVT());"
LLVM,RISCV,2771,}
LLVM,RISCV,2772,LLVMContext & Context = * DAG . getContext ( ) ;
LLVM,RISCV,2773,if (ImmValue >= <NUM_LIT>) {
LLVM,RISCV,2774,SDValue VL = Op . getOperand (1);
LLVM,RISCV,2775,
LLVM,RISCV,2776,"Ops.push_back(convertToScalableVector(ContainerVT, V, DAG, Subtarget));"
LLVM,RISCV,2777,"return convertFromScalableVector ( VT , VPOp , DAG , Subtarget ) ;"
LLVM,RISCV,2778,break ;
LLVM,RISCV,2779,
LLVM,RISCV,2780,
LLVM,RISCV,2781,}
LLVM,RISCV,2782,
LLVM,RISCV,2783,
LLVM,RISCV,2784,
LLVM,RISCV,2785,return true;
LLVM,RISCV,2786,}
LLVM,RISCV,2787,return Subtarget . is64Bit ( ) && CI -> getType ( ) -> isIntegerPtrTy ( <NUM_LIT> ) ;
LLVM,RISCV,2788,
LLVM,RISCV,2789,"return false. Then, it sets ElemVT to the element type of VT and checks if Alignment is greater than or equal to the store size of the element type. If so, it return false;"
LLVM,RISCV,2790,
LLVM,RISCV,2791,LLVM_DEBUG(dbgs() << <STR_LIT> << FirstMaskArgument << <STR_LIT> << ArgVT.isVector() << '\n');
LLVM,RISCV,2792,llvm_unreachable(nullptr);
LLVM,RISCV,2793,It . <NUM_LIT> ;
LLVM,RISCV,2794,
LLVM,RISCV,2795,
LLVM,RISCV,2796,"if ( SDValue Result = combineSelectCCAndUse ( N , N2 , N1 , DAG , AllOnes ) ) return Result ;"
LLVM,RISCV,2797,"if ( SDValue Result = combineSelectCCAndUse ( N , N2 , N2 , DAG , AllOnes ) ) return Result ;"
LLVM,RISCV,2798,Known.Zero.setLowBits(<NUM_LIT>);
LLVM,RISCV,2799,
LLVM,RISCV,2800,return false;
LLVM,RISCV,2801,
LLVM,RISCV,2802,
LLVM,RISCV,2803,
LLVM,RISCV,2804,
LLVM,RISCV,2805,
LLVM,RISCV,2806,"SDValue Result = convertToScalableVector(VT, NewLoad, DAG, Subtarget);"
LLVM,RISCV,2807,"'SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ContainerVT, Load, VL)'"
LLVM,RISCV,2808,}
LLVM,RISCV,2809,
LLVM,RISCV,2810,"SDNode *BuildLoad = DAG.getMachineNode(ISD::LOAD, DL, VTs, Ops);"
LLVM,RISCV,2811,"`VL = DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Index), VT, Index, DAG.getConstant(IsUnmasked, SDLoc(Index), MVT::i1));"
LLVM,RISCV,2812,"return DAG.getNode(<STR_LIT>, DL, Op.getValueType(), Ops);"
LLVM,RISCV,2813,
LLVM,RISCV,2814,if ( isConstantVecElts_64 ( StepVec ) ) {
LLVM,RISCV,2815,"GatherIndicesRHS.push_back(DAG.getConstant(std::numeric_limits<int>::max(), DL, XLenVT));"
LLVM,RISCV,2816,
LLVM,RISCV,2817,
LLVM,RISCV,2818,N = DAGRoot;
LLVM,RISCV,2819,
LLVM,RISCV,2820,}
LLVM,RISCV,2821,else {
LLVM,RISCV,2822,DCI.AddToWorklist(&N);
LLVM,RISCV,2823,"return combineRotateAndInsertBitField(N, DAG, Subtarget);"
LLVM,RISCV,2824,return true;
LLVM,RISCV,2825,break;
LLVM,RISCV,2826,if (Step != SeqStep) return None;
LLVM,RISCV,2827,
LLVM,RISCV,2828,"if ( CCVal != <STR_LIT> && CCVal != <STR_LIT> && CCVal != <STR_LIT> ) return DAG . getNode ( <STR_LIT> ( ) , DL , XLenVT , Ops ) ;"
LLVM,RISCV,2829,IndexVT = XLenVT ;
LLVM,RISCV,2830,
LLVM,RISCV,2831,"case <STR_LIT> : return emitCmpF64Pseudo ( MI , BB ) ;"
LLVM,RISCV,2832,return <STR_LIT> ;
LLVM,RISCV,2833,
LLVM,RISCV,2834,if ( Op0 . getOpcode ( ) == <STR_LIT> ) return ;
LLVM,RISCV,2835,
LLVM,RISCV,2837,"Result = DAG.getNode(ISD::BUILD_VECTOR, DL, ContainerVT, Src, Mask, VL);"
LLVM,RISCV,2838,
LLVM,RISCV,2839,
LLVM,RISCV,2840,
LLVM,RISCV,2841,
LLVM,RISCV,2842,
LLVM,RISCV,2843,}
LLVM,RISCV,2844,"( CallConv , IsVarArg , MF , RVLocs , Context ) ;"
LLVM,RISCV,2845,
LLVM,RISCV,2846,Reg = State . AllocateReg ( ArgVRM8s ) ;
LLVM,RISCV,2847,return SDValue();
LLVM,RISCV,2848,
LLVM,RISCV,2849,
LLVM,RISCV,2850,
LLVM,RISCV,2851,
LLVM,RISCV,2852,return <STR_LIT> ;
LLVM,RISCV,2853,
LLVM,RISCV,2854,
LLVM,RISCV,2855,
LLVM,RISCV,2856,"return SDValue::SDValue(EVT, uint64_t);"
LLVM,RISCV,2857,SDValue Base = Op . getOperand ( <NUM_LIT> ) ;
LLVM,RISCV,2858,SDLoc DL ( Op ) ;
LLVM,RISCV,2859,"Chain = SDValue(Glue, RVLocs);"
LLVM,RISCV,2860,
LLVM,RISCV,2861,"SDValue Result = DAG.getNode(CondCodeSDNode.get(), DL, Op.getValueType(), Ops);"
LLVM,RISCV,2862,auto NewMask = ( Src . getValueSizeInBits ( ) & ExpMask ) ;
LLVM,RISCV,2863,"return SDValue ( N , <NUM_LIT> ) ;"
LLVM,RISCV,2864,
LLVM,RISCV,2865,}
LLVM,RISCV,2866,SDNode * ValPtr = DAG.getMachineFunction().getNodePtr();
LLVM,RISCV,2867,"N = SelectionDAG :: getNode(ISD::INSERT_VECTOR_ELT, DL, NarrowVT, N->getOperand(0), Mask, VL)"
LLVM,RISCV,2868,
LLVM,RISCV,2869,if (ShAmt1 < 0) return SDValue();
LLVM,RISCV,2870,
LLVM,RISCV,2871,Op0 = Op0 . getOperand ( <NUM_LIT> + 1 ) ;
LLVM,RISCV,2872,
LLVM,RISCV,2873,
LLVM,RISCV,2874,
LLVM,RISCV,2875,"1.DAG.computeKnownBits(Op.getOperand(<NUM_LIT>), DemandedElts, Depth + <NUM_LIT>);"
LLVM,RISCV,2876,}
LLVM,RISCV,2877,
LLVM,RISCV,2878,"return DAG.getNode(<STR_LIT>, DL, Ty, AddrAdd, AddrLo, MNHi);"
LLVM,RISCV,2879,"Info . memVT = getTypeSizeInBits ( DL , I . getType ( ) -> getScalarType ( ) ) ;"
LLVM,RISCV,2880,return (X.getOpcode() == ISD::SETCC && X.getOperand(0).getOpcode() == ISD::AND && Y.getOpcode() == ISD::Constant );
LLVM,RISCV,2881,
LLVM,RISCV,2882,int & MaskTarget = StartIdx < Size ? LoTarget : HiTarget;
LLVM,RISCV,2883,assert ( Rotation != <NUM_LIT> && <STR_LIT> ) ;
LLVM,RISCV,2884,
LLVM,RISCV,2885,return false;
LLVM,RISCV,2886,"return isLerpCycle(M, SVT, Subtarget);"
LLVM,RISCV,2887,"SDValue Splat = DAG.getNode(<STR_LIT>, DL, VT, X, Mask, VL, SplatZero);"
LLVM,RISCV,2888,
LLVM,RISCV,2889,"SDValue Vec = DAG.getNode(, DL, ContainerVT, );"
LLVM,RISCV,2890,"SDValue IntID = DAG.getTargetConstant(IsMaskOp ? masked_store : store, DL, XLenVT);"
LLVM,RISCV,2891,"SDValue Reduce = DAG.getNode(RVVOpcode, DL, M1VT, DAG.getUNDEF(M1VT), VectorVal, ScalarSplat, Mask, VL);"
LLVM,RISCV,2892,
LLVM,RISCV,2893,"Truncated = DAG.getNode(<STR_LIT>, DL, VT, Truncated, Src);"
LLVM,RISCV,2894,MaxVal . getNextToward(APFloat::getZero(false)) ;
LLVM,RISCV,2895,"Truncated = DAG.getNode(pAdd, DL, VT, Truncated, MaxValNode);"
LLVM,RISCV,2896,return ValInVec;
LLVM,RISCV,2897,return SDValue ( }
LLVM,RISCV,2898,
LLVM,RISCV,2899,"SDValue XLenMinus1Minus1 = DAG.getNode(<STR_LIT>, DL, VT, XLenMinus1, One);"
LLVM,RISCV,2900,"SDValue MinusXLen1 = DAG.getNode(ShiftLeftOp, DL, VT, ShiftRightLo, ShiftLeftHi);"
LLVM,RISCV,2901,"SDValue ShiftOp = DAG.getNode(ShiftRightOp, DL, VT, Hi, ShamtMinusXLen);"
LLVM,RISCV,2902,
LLVM,RISCV,2903,if (Hi.getOpcode() == <STR_LIT> && Hi.getOperand(<NUM_LIT>) == Lo && isa<ConstantSDNode>(Hi.getOperand(<NUM_LIT>)) && Hi.getConstantOperandVal(<NUM_LIT>) == <NUM_LIT>) {
LLVM,RISCV,2904,"SDValue StepVal = lowerScalarSplat (SDValue(), DAG.getConstant(StepValImm + 1, DL, VT.getVectorElementType()), VL, VT, DL, DAG, Subtarget);"
LLVM,RISCV,2905,SDValue NextVal = DAG.getValue(StepVec);
LLVM,RISCV,2906,SDValue Vec = Op.getOperand(1);
LLVM,RISCV,2907,return {
LLVM,RISCV,2908,"SplatTrueVal = DAG.getNode(<STR_LIT>, DL, ContainerVT, DAG.getUNDEF(ContainerVT), SplatTrueVal, VL);"
LLVM,RISCV,2909,if ( VecVT . isScalableVector ( ) ) {
LLVM,RISCV,2910,"SDValue MaskResult = DAG.getNode(<STR_LIT>, DL, ContainerVT, Trunc, SplatOne, Mask, VL);"
LLVM,RISCV,2911,"SDValue IDX = DAG.getNode(GatherOpc, DL, MVT::Other, SplatVL, VID);"
LLVM,RISCV,2912,
LLVM,RISCV,2913,<NUM_LIT>){
LLVM,RISCV,2914,"Src = DAG . getNode ( <STR_LIT> , DL , InterimFVT , {"
LLVM,RISCV,2915,return Reduction;
LLVM,RISCV,2916,"return SDValue( getNode(SDNode <ID> , SDLoc(N), ContainerVT, {"
LLVM,RISCV,2917,return Gather;
LLVM,RISCV,2918,
LLVM,RISCV,2919,"SDValue Res = SDValue::getNode (ISD :: SIGN_EXTEND, SDLoc(N), VT, Src);"
LLVM,RISCV,2920,
LLVM,RISCV,2921,
LLVM,RISCV,2922,case Instruction :: InsertElt: return true ;
LLVM,RISCV,2923,"return DAG.getNode(<STR_LIT>, DL, VT, Passthru, Lo, Hi, VL);"
LLVM,RISCV,2924,
LLVM,RISCV,2925,"return concatPartsI64WithVL ( DL , VT , Passthru , Lo , Hi , VL , DAG ) ;"
LLVM,RISCV,2926,"if ( ! UseGPRForF64 ) Reg = State . AllocateReg ( ArgFPR64s , ArgFPR16s ) ;"
LLVM,RISCV,2927,"Val = DAG.getNode(<STR_LIT>, DL, VA.getValVT(), Val);"
LLVM,RISCV,2928,"Val = DAG.getNode(STR_LIT, DL, VA.getValVT(), Val);"
LLVM,RISCV,2929,}
LLVM,RISCV,2930,
LLVM,RISCV,2931,
LLVM,RISCV,2932,"BuildMI(*BB, MI, DL, TII.get(<STR_LIT>)).addReg(DstReg, getKillRegState(MI.getOperand(<NUM_LIT>).isKill())).addFrameIndex(FI).addImm(<NUM_LIT>).addMemOperand(MMO);"
LLVM,RISCV,2933,llvm_unreachable(<STR_LIT>);
LLVM,RISCV,2934,Register HiReg = MI.getOperand(<NUM_LIT>).getReg();
LLVM,RISCV,2935,
LLVM,RISCV,2936,if (EltVT.getScalarType() != VecVT.getScalarType()) return Op;
LLVM,RISCV,2937,EVT EltVT = VecVT .getVectorElementType();
LLVM,RISCV,2938,"return DAG.getNode(<STR_LIT>, DL, Op.getValueType(), {"
LLVM,RISCV,2939,
LLVM,RISCV,2940,"SDValue Lo = GetElt ( ), SDValue Hi = GetElt ( );"
LLVM,RISCV,2941,"return lowerSETCC ( Op , DAG ) ;"
LLVM,RISCV,2942,case <STR_LIT> : assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && Subtarget . hasStdExtM ( ) && <STR_LIT> ) ;
LLVM,RISCV,2943,
LLVM,RISCV,2944,break;
LLVM,RISCV,2945,return false;
LLVM,RISCV,2946,
LLVM,RISCV,2947,"return emitSplitF64Pseudo ( MI , BB ) ;"
LLVM,RISCV,2948,"return emitBuildPairI64Pseudo (MI, BB);"
LLVM,RISCV,2949,
LLVM,RISCV,2950,"Value* Result = Builder.CreateCall(MaskedCmpXchg, {"
LLVM,RISCV,2951,"Builder.CreateCall(LrwOpScwLoop, {"
LLVM,RISCV,2952,return Result;
LLVM,RISCV,2953,return Load;
LLVM,RISCV,2954,"likely include the function call SDValue::setValue (Load, Args) to set the value of Load and Args."
LLVM,RISCV,2955,
LLVM,RISCV,2956,if (Subtarget.getTargetABI() == ABI::SysV) return R8;
LLVM,RISCV,2957,
LLVM,RISCV,2958,
LLVM,RISCV,2959,
LLVM,RISCV,2960,
LLVM,RISCV,2961,return TailPaddingAmount::Default;
LLVM,RISCV,2962,return true ;
LLVM,RISCV,2963,BlockAddressSDNode *nextNode = getNextNode(N);
LLVM,RISCV,2964,}
LLVM,RISCV,2965,"return DAG.getNode(<STR_LIT>, DL, Op.getValueType(), Op, Op. getOperand(<NUM_LIT>).getNextNode(), LHS, RHS, TargetCC, Op. getOperand(<NUM_LIT>));"
LLVM,RISCV,2966,ConstantPoolSDNode * NextN = cast < ConstantPoolSDNode > (N.getNextNode());
LLVM,RISCV,2967,
LLVM,RISCV,2968,"if (Offset != <NUM_LIT>) return DAG.getPointerAdd(DL, Addr, Offset);"
LLVM,RISCV,2969,
LLVM,RISCV,2970,
LLVM,RISCV,2971,if ( IsMasked ){
LLVM,RISCV,2972,
LLVM,RISCV,2973,
LLVM,RISCV,2974,
LLVM,RISCV,2975,"return DAG.getNode(<STR_LIT>, DL, Op.getValueType(), Ops);"
LLVM,RISCV,2976,
LLVM,RISCV,2977,
LLVM,RISCV,2978,return SDValue();
LLVM,RISCV,2979,return AtomicExpansionKind :: None ;
LLVM,RISCV,2980,return AtomicExpansionKind::UnmaskedIntrinsic;
LLVM,RISCV,2981,
LLVM,RISCV,2982,
LLVM,RISCV,2983,
LLVM,RISCV,2984,Val = FIN.getValue(0);
LLVM,RISCV,2985,"The next statement of this code snippet could be a return statement returning a boolean value, comparing an operand with a '*'. For example: return operand == '*';"
LLVM,RISCV,2986,
LLVM,RISCV,2987,
LLVM,RISCV,2988,}
LLVM,RISCV,2989,
LLVM,RISCV,2990,
LLVM,RISCV,2991,case <STR_LIT> : {
LLVM,RISCV,2992,"BuildMI(*TailMBB, InsertionPoint, SelectMBBI->getDebugLoc(), TII.get(<STR_LIT>), SelectMBBI->getOperand(<NUM_LIT>).getReg()).addReg(SelectMBBI->getOperand(<NUM_LIT>).getReg()).addMBB(TailMBB).addReg(SelectMBBI->getOperand(<NUM_LIT>).getReg()).addMBB(IfFalseMBB);"
LLVM,RISCV,2993,default: return
LLVM,RISCV,2994,EVT VT = DAG.getVTList(Index.getNode()->getValueType(0)).getValueType(0);
LLVM,RISCV,2995,
LLVM,RISCV,2996,"setOperationAction ( <STR_LIT> , XLenVT , Expand ) ;"
LLVM,RISCV,2997,"Another repeat of setOperationAction ( <STR_LIT> , XLenVT , Expand ) ;"
LLVM,RISCV,2998,
LLVM,RISCV,2999,
LLVM,RISCV,3000,assert ( VA . isMemLoc ( ) && Expected a memory location) ;
LLVM,RISCV,3001,SDValue GlueVal = SplitF64.getValue(1);
LLVM,RISCV,3002,llvm_unreachable(nullptr);
LLVM,RISCV,3003,
LLVM,RISCV,3004,
LLVM,RISCV,3005,"if ( CC_<ISA_LIT> ( MF.getDataLayout(), e, VT, CCValAssign::Full, ArgFlags, CCInfo, true, true ) ) return true;"
LLVM,RISCV,3006,
LLVM,RISCV,3007,return VA . getLocVT ( ) ;
LLVM,RISCV,3008,"DAG.getStore(VA.getLocReg(), DL, Val, Chain, <NUM_LIT>);"
LLVM,RISCV,3009,"setOperationAction ( <STR_LIT> , XLenVT , Expand ) ;"
LLVM,RISCV,3010,
LLVM,RISCV,3011,"return SDValue(DAG.getMachineNode(<STR_LIT>, DL, Ty, MNHi, AddrLo), <NUM_LIT>);"
LLVM,RISCV,3012,
LLVM,RISCV,3013,return DAG.getTargetBlockAddress(N);
LLVM,RISCV,3014,return 0;
LLVM,RISCV,3015,
LLVM,RISCV,3016,
LLVM,RISCV,3017,"return lowerShiftRightParts ( Op , DAG ) ;"
LLVM,RISCV,3018,"Prediction: BuildMI(*BB, MI, DL, TII.get(<STR_LIT>)).addReg(DestReg, RegState::Define | RegState::Dead).addReg(VLReg) return BuildMI(*BB, MI, DL, TII.get(<STR_LIT>)).addReg(<STR_LIT>, RegState::Define | RegState::Dead).addReg(<STR_LIT>, RegState::Kill);"
LLVM,RISCV,3019,}
LLVM,RISCV,3020,
LLVM,RISCV,3021,
LLVM,RISCV,3022,
LLVM,RISCV,3023,Predict the next statement of this code snippet:
LLVM,RISCV,3024,
LLVM,RISCV,3025,
LLVM,RISCV,3026,"> getArrayElementType() , SDValue (LoC , DL ) , SDValue (cast < ConstantSDNode > (Hi ) -> getSExtValue() , DL) ) , 0);"
LLVM,RISCV,3027,}
LLVM,RISCV,3028,return SDValue(NewOp0);
LLVM,RISCV,3029,"SDValue NewOp1 = DAG.getNode(<STR_LIT>, DL, MVT::f32, NewOp0);"
LLVM,RISCV,3030,default : break ;
LLVM,RISCV,3031,
LLVM,RISCV,3032,"setOperationAction ( <STR_LIT> , BF16VT , Expand ) ;"
LLVM,RISCV,3033,"<STR_LIT>, <STR_LIT>, <STR_LIT> }"
LLVM,RISCV,3034,
LLVM,RISCV,3035,}
LLVM,RISCV,3036,
LLVM,RISCV,3037,}
LLVM,RISCV,3038,"N->getOperand(<NUM_LIT>).getOpcode() == <STR_LIT> ? Results.push_back(customLegalizeToWOp(N, DAG)) : Results.push_back(customLegalizeToWOpWithSExt(N, DAG));"
LLVM,RISCV,3039,
LLVM,RISCV,3040,SDValue Ops <STR_LIT> = {
LLVM,RISCV,3041,
LLVM,RISCV,3042,
LLVM,RISCV,3043,SDValue Container = Val;
LLVM,RISCV,3044,else {
LLVM,RISCV,3045,return V ;
LLVM,RISCV,3046,if (Op != nullptr) {
LLVM,RISCV,3047,
LLVM,RISCV,3048,break;
LLVM,RISCV,3049,default: return nullptr;
LLVM,RISCV,3050,
LLVM,RISCV,3051,"return lowerVARARG ( Op , DAG ) ;"
LLVM,RISCV,3052,Results.push_back(Res.getValue(I + 1));
LLVM,RISCV,3053,Results.push_back(Res);
LLVM,RISCV,3054,
LLVM,RISCV,3055,"return DAG.getNode(ISD::BUILD_VECTOR, DL, Ty, V1, V2);"
LLVM,RISCV,3056,"SDValue finalResult = DAG.getNode(<STR_LIT>, DL, RegTy, rawResult, mask);"
LLVM,RISCV,3057,
LLVM,RISCV,3058,case <STR_LIT> : {
LLVM,RISCV,3059,
LLVM,RISCV,3060,"setOperationAction( <STR_LIT> , <STR_LIT> , Custom );"
LLVM,RISCV,3061,"setOperationAction(<STR_LIT>, <STR_LIT>, Custom) ;"
LLVM,RISCV,3062,"setOperationAction ( <STR_LIT> , XLenVT , Custom ) ;"
LLVM,RISCV,3063,}
LLVM,RISCV,3064,}
LLVM,RISCV,3065,
LLVM,RISCV,3066,
LLVM,RISCV,3067,}
LLVM,RISCV,3068,break;
LLVM,RISCV,3069,
LLVM,RISCV,3070,
LLVM,RISCV,3071,
LLVM,RISCV,3072,"return DAG.getNode(<STR_LIT>, DL, SetCCVT, VID, SplattedVal, SplattedIdx);"
LLVM,RISCV,3073,"case <STR_LIT> : return LowerSELECT_CC(Op, DAG);"
LLVM,RISCV,3074,"return lowerVectorMaskExt ( Op , DAG , <NUM_LIT> ) ;"
LLVM,RISCV,3075,"Hi = DAG . getNode ( <STR_LIT> , DL , VecVT , Hi , ThirtyTwoV ) ;"
LLVM,RISCV,3076,if (isNullConstant ( Hi ) ) {
LLVM,RISCV,3077,"SplatZero = DAG . getSplatVector ( VecVT , DL , SplatZero ) ;"
LLVM,RISCV,3078,"SplatOne = DAG . getBuildVector ( VecVT , DL , {"
LLVM,RISCV,3079,"return TLO.CombineTo(Op, NewOp);"
LLVM,RISCV,3080,"return DCI . CombineTo ( N , DAG . getNode ( N -> getOpcode ( ) , DL , Src . getValueType ( ) , Src , NewRHS ) ) ;"
LLVM,RISCV,3081,case <NUM_LIT> : {
LLVM,RISCV,3082,return false ;
LLVM,RISCV,3083,assert ( ValueVTs [ <NUM_LIT> ] == <STR_LIT> ) ;
LLVM,RISCV,3084,
LLVM,RISCV,3085,
LLVM,RISCV,3086,
LLVM,RISCV,3087,
LLVM,RISCV,3088,if (imm2 + imm3 <= <NUM_LIT>) {
LLVM,RISCV,3089,newMI . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ;
LLVM,RISCV,3090,
LLVM,RISCV,3091,
LLVM,RISCV,3092,}
LLVM,RISCV,3093,"case 'f' : if ( Subtarget . is64Bit ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ;"
LLVM,RISCV,3094,
LLVM,RISCV,3095,<std::cout << Code execution completed. </std>
LLVM,RISCV,3096,}
LLVM,RISCV,3097,unsigned new_var = pred & succ;
LLVM,RISCV,3098,
LLVM,RISCV,3099,RetOps.push_back(Glue);
LLVM,RISCV,3100,}
LLVM,RISCV,3101,
LLVM,RISCV,3102,
LLVM,RISCV,3103,if ( VT == MVT::Other ) VT = (Prefix == lo || Prefix == hi) ? MVT::i32 : MVT::i64;
LLVM,RISCV,3104,"Reg . changeToRegister ( C . get ( ) , <STR_LIT> , false ) ;"
LLVM,RISCV,3105,"DAG . computeKnownBits ( Op -> getOperand ( <NUM_LIT> ) , Known3 , Depth + <NUM_LIT> ) ;"
LLVM,RISCV,3106,
LLVM,RISCV,3107,
LLVM,RISCV,3108,"return lowerSETVLX ( Op , DAG );"
LLVM,RISCV,3109,
LLVM,RISCV,3110,"return lowerFRAMEADDJUST ( Op , DAG );"
LLVM,RISCV,3111,"SDValue Result = DAG.getNode(RISCVISD::ADD, DL, ResultVTs, Op, Op);"
LLVM,RISCV,3112,"RegisterSDNode *New = DAG.getRegister(XLenVT, 0);"
LLVM,RISCV,3113,return SDValue();
LLVM,RISCV,3114,}
LLVM,RISCV,3115,
LLVM,RISCV,3116,
LLVM,RISCV,3117,llvm_unreachable ( <STR_LIT> ) ;
LLVM,RISCV,3118,}
LLVM,RISCV,3119,"getPointerTy(DL) : <STR_LIT>(<STR_LIT>, VT.getVectorElementCount()) : VT.changeVectorElementTypeToInteger();"
LLVM,RISCV,3120,"return GetVectorRegisterType(VT, DL, VT.getVectorElementCount());"
LLVM,RISCV,3121,}
LLVM,RISCV,3122,
LLVM,RISCV,3123,
LLVM,RISCV,3124,"return lowerUINT_TO_FP ( Op , DAG ) ;"
LLVM,RISCV,3125,
LLVM,RISCV,3126,"Lo = DAG.getNode(<STR_LIT>, DL, VecVT, Lo, Zero);"
LLVM,RISCV,3127,Possible output:
LLVM,RISCV,3128,if ( MVT :: isInteger
LLVM,RISCV,3129,return <NUM_LIT> ;
LLVM,RISCV,3130,return false;
LLVM,RISCV,3131,return false ;
LLVM,RISCV,3132,return false;
LLVM,RISCV,3133,}
LLVM,RISCV,3134,"Value = DAG . getNode ( GVA , DL , VA . getValVT ( ) , Value ) ;"
LLVM,RISCV,3135,
LLVM,RISCV,3136,"default: return emitRequest ( MI , MBB ) ;"
LLVM,RISCV,3137,break;
LLVM,RISCV,3138,
LLVM,RISCV,3139,"return DAG . getNode ( <NUM_LIT> , MVT :: Other , {"
LLVM,RISCV,3140,if ( IsRet ) ArgTy = FType -> getReturnType ( ) ;
LLVM,RISCV,3141,
LLVM,RISCV,3142,"State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , StackOffset , LocVT , LocInfo ) ) ;"
LLVM,RISCV,3143,"State . addLoc ( CCValAssign :: getMem ( ValNo2 , ValVT2 , State . AllocateStack ( XLenInBytes , StackAlign ) , LocVT2 , CCValAssign :: Full ) ) ;"
LLVM,RISCV,3144,break ;
LLVM,RISCV,3145,"Val = DAG.getNode(<STR_LIT>, DL, VA.getValVT(), Val);"
LLVM,RISCV,3146,"in the switch case CCValAssign :: BCvt, create a node of <STR_LIT> with the given variables and assign it to Val. After that, the switch case statement is terminated."
LLVM,RISCV,3147,
LLVM,RISCV,3148,if (XLen == {
LLVM,RISCV,3149,"Function *MaskedCmpXchg = Builder.CreateCall(MaskedCmpXchg, {"
LLVM,RISCV,3150,
LLVM,RISCV,3151,
LLVM,RISCV,3152,else return nullptr;
LLVM,RISCV,3153,return Builder.CreateFence(AtomicOrdering::Release);
LLVM,RISCV,3154,case AtomicRMWInst :: Max : return <STR_LIT> ;
LLVM,RISCV,3155,
LLVM,RISCV,3156,"return std::make_pair(llvm::ARM::R0, &PPC::G8RCRegClass);"
LLVM,RISCV,3157,}
LLVM,RISCV,3158,}
LLVM,RISCV,3159,return VT;
LLVM,RISCV,3160,return <STR_LIT> ;
LLVM,RISCV,3161,
LLVM,RISCV,3162,
LLVM,RISCV,3163,if (IsCallerStructRet && !IsCalleeStructRet) return false;
LLVM,RISCV,3164,
LLVM,RISCV,3165,return false;
LLVM,RISCV,3166,}
LLVM,RISCV,3167,return (SrcVT.getSizeInBits() > DstVT.getSizeInBits());
LLVM,RISCV,3168,
LLVM,RISCV,3169,return false;
LLVM,RISCV,3170,
LLVM,RISCV,3171,else if ( auto * C = dyn_cast < ConstantFP < Duty cycle / Mining fee = Low> ( Val ) const {
LLVM,RISCV,3172,
LLVM,RISCV,3173,ArrayRef<MCPhysReg> ArgRegs = makeArrayRef(ArgGPRs);
LLVM,RISCV,3174,ArgRegs [ I ] = -1 ;
LLVM,RISCV,3175,"FrameAddr = DAG.getLoad(VT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo());"
LLVM,RISCV,3176,unsigned Depth = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
LLVM,RISCV,3177,
LLVM,RISCV,3178,
LLVM,RISCV,3179,"return lowerVACOPY ( Op , DAG ) ;"
LLVM,RISCV,3180,SDValue Undef = DAG . getUNDEF ( VT ) ;
LLVM,RISCV,3181,
LLVM,RISCV,3182,"return DAG.getNode(ISD::SETCC, DL, VTs, LHS, RHS, TargetCC);"
LLVM,RISCV,3183,
LLVM,RISCV,3184,return SDValue::uninitialized();
LLVM,RISCV,3185,
LLVM,RISCV,3186,if (Subtarget.hasStdExtM() && isVariableSDivUDivURem(Src)) {
LLVM,RISCV,3187,
LLVM,RISCV,3188,}
LLVM,RISCV,3189,If (Size == <NUM_LIT>) {
LLVM,RISCV,3190,std::cout << an if statement checking if CI is null.
LLVM,RISCV,3191,
LLVM,RISCV,3192,"Hi = DAG . getCopyFromReg ( Chain , DL , HiVReg , <STR_LIT> ) ;"
LLVM,RISCV,3193,MFI.setStackAlignment(PtrVT);
LLVM,RISCV,3194,
LLVM,RISCV,3195,
LLVM,RISCV,3196,something along the lines of: - for (int i = 0;
LLVM,RISCV,3197,
LLVM,RISCV,3198,}
LLVM,RISCV,3199,}
LLVM,RISCV,3200,}
LLVM,RISCV,3201,
LLVM,RISCV,3202,
LLVM,RISCV,3203,
LLVM,RISCV,3204,}
LLVM,RISCV,3205,
LLVM,RISCV,3206,
LLVM,RISCV,3207,
LLVM,RISCV,3208,
LLVM,RISCV,3209,return_ppc ();
LLVM,RISCV,3210,
LLVM,RISCV,3211,
LLVM,RISCV,3212,}
LLVM,RISCV,3213,}
LLVM,RISCV,3214,return MF.getProperties().getNextFrameIndex();
LLVM,RISCV,3215,
LLVM,RISCV,3216,
LLVM,RISCV,3217,return HwlpBasicBlocks.entry();
LLVM,RISCV,3218,
LLVM,RISCV,3219,
LLVM,RISCV,3220,return MF.getInfo();
LLVM,RISCV,3221,}
LLVM,RISCV,3222,
LLVM,RISCV,3223,
LLVM,RISCV,3224,return manipulatesSP;
LLVM,RISCV,3225,return manipulatesSP ;
LLVM,RISCV,3226,
LLVM,RISCV,3227,}
LLVM,RISCV,3228,
LLVM,RISCV,3229,
LLVM,RISCV,3230,int main() {
LLVM,RISCV,3231,
LLVM,RISCV,3232,
LLVM,RISCV,3233,
LLVM,RISCV,3234,
LLVM,RISCV,3235,
LLVM,RISCV,3236,if ( HasByval ) {
LLVM,RISCV,3237,}
LLVM,RISCV,3238,return Reg;
LLVM,RISCV,3239,counter1 ++;
LLVM,RISCV,3240,}
LLVM,RISCV,3241,}
LLVM,RISCV,3242,
LLVM,RISCV,3243,return FPR;
LLVM,RISCV,3244,VarArgsFirstGPR = VarArgsFirstGPR + 1 ;
LLVM,RISCV,3245,
LLVM,RISCV,3246,
LLVM,RISCV,3247,
LLVM,RISCV,3248,MF.getFrameInfo().ensureMaxAlignment(Align);
LLVM,RISCV,3249,
LLVM,RISCV,3250,X.nextVarArgsFrameIndex = yamlMFI.X.nextVarArgsFrameIndex;
LLVM,RISCV,3251,return;
LLVM,RISCV,3252,an opening brace {
LLVM,RISCV,3253,null }
LLVM,RISCV,3254,value = VarArgsFrameIndex[index];
LLVM,RISCV,3255,}
LLVM,RISCV,3256,
LLVM,RISCV,3257,RCToScavenge = & <STR_LIT> ;
LLVM,RISCV,3258,return CompressedLDSTOffsetMaskTable[Opcode & 15];
LLVM,RISCV,3259,
LLVM,RISCV,3260,}
LLVM,RISCV,3261,return Offset + Opcode;
LLVM,RISCV,3262,return Offset >> ((Opcode - 1) & 0x1f);
LLVM,RISCV,3263,
LLVM,RISCV,3264,
LLVM,RISCV,3265,}
LLVM,RISCV,3266,throw new Exception(isCompressedReg() not implemented);
LLVM,RISCV,3267,
LLVM,RISCV,3268,if (Opcode == LOAD) {
LLVM,RISCV,3269,
LLVM,RISCV,3270,
LLVM,RISCV,3271,
LLVM,RISCV,3272,
LLVM,RISCV,3273,
LLVM,RISCV,3274,assert (isCompressibleLoad(MI));
LLVM,RISCV,3275,return Opc + Imm;
LLVM,RISCV,3276,
LLVM,RISCV,3277,
LLVM,RISCV,3278,"Res.push_back(Inst(SLT, ShiftAmount));"
LLVM,RISCV,3279,"check if the condition (LeadingZeros == <NUM_LIT> && ActiveFeatures [ <STR_LIT> ]) is true, and if so, it"
LLVM,RISCV,3280,
LLVM,RISCV,3281,}
LLVM,RISCV,3282,
LLVM,RISCV,3283,"Res . push_back ( <STR_LIT> ( <NUM_LIT> , Lo12 ) ) ;"
LLVM,RISCV,3284,MatSeq.execute();
LLVM,RISCV,3285,}
LLVM,RISCV,3286,
LLVM,RISCV,3287,
LLVM,RISCV,3288,
LLVM,RISCV,3289,"generateInstSeq(Lo12, IsRV64, Res);"
LLVM,RISCV,3290,
LLVM,RISCV,3291,MatSeq.push_back(Chunk);
LLVM,RISCV,3292,
LLVM,RISCV,3293,return <NUM_LIT> - UpperTrailingOnes ;
LLVM,RISCV,3294,
LLVM,RISCV,3295,"generateInstSeqImpl ( Val / Div , ActiveFeatures , TmpSeq ) ;"
LLVM,RISCV,3296,return Res;
LLVM,RISCV,3297,return Cost ;
LLVM,RISCV,3298,
LLVM,RISCV,3299,assert ( ActiveFeatures [ \and\ ] && \or\ ) ;
LLVM,RISCV,3300,
LLVM,RISCV,3301,"generateInstSeqImpl ( Val , ActiveFeatures , TmpSeq ) ;"
LLVM,RISCV,3302,
LLVM,RISCV,3303,break ;
LLVM,RISCV,3304,if ( Opc == <NUM_LIT> ) {
LLVM,RISCV,3305,assert ( IsRV64 && <STR_LIT> ) ;
LLVM,RISCV,3306,case <STR_LIT> : Compressed = false ;
LLVM,RISCV,3307,"return std::max(0, Cost);"
LLVM,RISCV,3308,to close the for loop by using }
LLVM,RISCV,3309,return the value of Infos[Kind - FirstTargetFixupKind] in the function <ISA_LIT>MCAsmBackend :: applyFixup.
LLVM,RISCV,3310,
LLVM,RISCV,3311,"return new ISA_MCMAsmBackend(T, MRI, TT, CPU);"
LLVM,RISCV,3312,Value <<= <NUM_LIT> ;
LLVM,RISCV,3313,Fixup = Fixup + 1;
LLVM,RISCV,3314,
LLVM,RISCV,3315,assert ( Opcode && <STR_LIT> ) ;
LLVM,RISCV,3316,
LLVM,RISCV,3317,
LLVM,RISCV,3318,return;
LLVM,RISCV,3319,IncludeDebugInfo = true ;
LLVM,RISCV,3320,return nullptr;
LLVM,RISCV,3321,
LLVM,RISCV,3322,Data64bitsDirective = <STR_LIT> ;
LLVM,RISCV,3323,
LLVM,RISCV,3324,(}
LLVM,RISCV,3325,
LLVM,RISCV,3326,UniqueIdentifier = <STR_LIT> ;
LLVM,RISCV,3327,Text: SupportsDebugInformation is set to true.
LLVM,RISCV,3328,<CALL_LIT>initFeatures ( TT ) ;
LLVM,RISCV,3329,<return MCAsmInfo(TT);
LLVM,RISCV,3330,CodePointerSize = TT.isArch64Bit() ? 8 : 4;
LLVM,RISCV,3331,AdditionalFlagsDirective = <code> After  Data64bitsDirective = <STR_LIT> ;
LLVM,RISCV,3332,TmpInst = MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( Ra ) . addImm ( <NUM_LIT> ) ;
LLVM,RISCV,3333,MI . getOperand ( i + <NUM_LIT> ) . setImm ( <NUM_LIT> << <NUM_LIT> ) ;
LLVM,RISCV,3334,}
LLVM,RISCV,3335,break;
LLVM,RISCV,3336,
LLVM,RISCV,3337,"uint16_t Bits = getBinaryCodeForInstr ( MI , Fixups , STI ) ;"
LLVM,RISCV,3338,
LLVM,RISCV,3339,"Fixups.push_back(MCFixup::create(<NUM_LIT>, Dummy, MCFixupKind(<STR_LIT>), MI.getLoc()));"
LLVM,RISCV,3340,Binary = MI.getOperand(<NUM_LIT>).getImm();
LLVM,RISCV,3341,FixupKind = <STR_LIT> ;
LLVM,RISCV,3342,"Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ;"
LLVM,RISCV,3343,return;
LLVM,RISCV,3344,break ;
LLVM,RISCV,3345,}
LLVM,RISCV,3346,
LLVM,RISCV,3347,}
LLVM,RISCV,3348,
LLVM,RISCV,3349,"The assert statement is checking that SrcSymbol is an expression of type <ISA_LIT>MCExpr and that the expression's kind is VK_<ISA_LIT>_TPREL_ADD . This is then followed by the line: Fixups.push_back( MCFixup:: create(<NUM_LIT>, Expr, MCFixupKind(<STR_LIT>), MI.getLoc() ) ) ;"
LLVM,RISCV,3350,
LLVM,RISCV,3351,
LLVM,RISCV,3352,either TmpInst = MCInstBuilder(<STR_LIT>).addReg(<STR_LIT>).addReg(Ra).addImm(<NUM_LIT>) ;
LLVM,RISCV,3353,FixupKind = <STR_LIT> ;
LLVM,RISCV,3354,case <STR_LIT>: return <NUM_LIT>;
LLVM,RISCV,3355,}
LLVM,RISCV,3356,
LLVM,RISCV,3357,FixupKind = <STR_LIT> ;
LLVM,RISCV,3358,<e> }
LLVM,RISCV,3359,
LLVM,RISCV,3360,Size = 0;
LLVM,RISCV,3361,}
LLVM,RISCV,3362,
LLVM,RISCV,3363,"uint16_t Bits = unsigned ( getBinaryCodeForInstr ( MI , Fixups , STI ) ) ;"
LLVM,RISCV,3364,break ;
LLVM,RISCV,3365,FixupKind = <STR_LIT> ;
LLVM,RISCV,3366,FixupKind = <STR_LIT> ;
LLVM,RISCV,3367,Assert ( FixupKind != <STR_LIT> && <STR_LIT> ) ;
LLVM,RISCV,3368,}
LLVM,RISCV,3369,"<STR_LIT> :: write ( OS , Binary , <STR_LIT> ) ;"
LLVM,RISCV,3370,"Binary = getBinaryCodeForInstr (TmpInst, Fixups, STI);"
LLVM,RISCV,3371,
LLVM,RISCV,3372,case <MPLZ_LIT> : FixupKind = <MPLZ_LIT> ;
LLVM,RISCV,3373,}
LLVM,RISCV,3374,"return new ISA_LITMCCodeEmitter(MCII, MRI, Ctx);"
LLVM,RISCV,3375,
LLVM,RISCV,3376,
LLVM,RISCV,3377,
LLVM,RISCV,3378,return <NUM_LIT>;
LLVM,RISCV,3379,
LLVM,RISCV,3380,return MO.getImm() << NUM_LIT;
LLVM,RISCV,3381,If (MO.isExpr()) {
LLVM,RISCV,3382,if ( MO .isReg ( ) ) return Ctx . getRegisterInfo ( ) -> getRegUnit ( MO . getReg ( ) ) ;
LLVM,RISCV,3383,else if ( MO . isImm ( ) ) return MO . getImm ( ) ;
LLVM,RISCV,3384,return MO.getImm() << <NUM_LIT> << <NUM_LIT>;
LLVM,RISCV,3385,MO . getImm(current value) << <NUM_LIT>;
LLVM,RISCV,3386,return MO.getImm();
LLVM,RISCV,3387,"return MCBinaryExpr::createAdd(Expr, MCConstantExpr::create(Offset, true), Ctx);"
LLVM,RISCV,3388,if (Expr) {
LLVM,RISCV,3389,"return finishEncodingInstruction(N,Address,getCurBuffer());"
LLVM,RISCV,3390,
LLVM,RISCV,3391,
LLVM,RISCV,3392,
LLVM,RISCV,3393,
LLVM,RISCV,3394,"Binary = getBinaryCodeForInstr (MI, Fixups, STI);"
LLVM,RISCV,3395,
LLVM,RISCV,3396,
LLVM,RISCV,3397,"Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);"
LLVM,RISCV,3398,
LLVM,RISCV,3399,"return new <ISA_LIT>MCCodeEmitter ( Ctx , MCII ) ;"
LLVM,RISCV,3400,"int16_t Bits = getBinaryCodeForInstr ( MI , Fixups , STI ) ;"
LLVM,RISCV,3401,
LLVM,RISCV,3402,
LLVM,RISCV,3403,break ;
LLVM,RISCV,3404,<ISA_LIT>MCInst NewMI ;
LLVM,RISCV,3405,
LLVM,RISCV,3406,"llvm_unreachable(Error: Expected immediate value, got other operand type);"
LLVM,RISCV,3407,
LLVM,RISCV,3408,
LLVM,RISCV,3409,
LLVM,RISCV,3410,
LLVM,RISCV,3411,"return new ISA::MCExpr(Kind, Expr, Ctx);"
LLVM,RISCV,3412,if ( ! Value . isInteger ( ) ) return false ;
LLVM,RISCV,3413,break;
LLVM,RISCV,3414,"calculate the AUIPCOffset by getting the offset of the AUIPCSymbol, then it"
LLVM,RISCV,3415,return nullptr;
LLVM,RISCV,3416,
LLVM,RISCV,3417,"<ISA_LIT>MCExpr :: VariantKind <ISA_LIT>MCExpr :: substituteValueInPlace ( const MCExpr * <Placeholder> , MCSymbolELF const * <Placeholder> , MCStreamer & OS ) const {"
LLVM,RISCV,3418,
LLVM,RISCV,3419,
LLVM,RISCV,3420,
LLVM,RISCV,3421,return NULL;
LLVM,RISCV,3422,
LLVM,RISCV,3423,
LLVM,RISCV,3424,
LLVM,RISCV,3425,
LLVM,RISCV,3426,return true;
LLVM,RISCV,3427,break;
LLVM,RISCV,3428,case MCExpr :: SymbolRef : {
LLVM,RISCV,3429,
LLVM,RISCV,3430,
LLVM,RISCV,3431,
LLVM,RISCV,3432,
LLVM,RISCV,3433,OS << '=VK_<ISA_LIT>_PUSH_EAX';
LLVM,RISCV,3434,}
LLVM,RISCV,3435,
LLVM,RISCV,3436,
LLVM,RISCV,3437,
LLVM,RISCV,3438,
LLVM,RISCV,3439,case VK_<ISA_LIT>_CALL_PLT : return <STR_LIT> ;
LLVM,RISCV,3440,`}
LLVM,RISCV,3441,}
LLVM,RISCV,3442,
LLVM,RISCV,3443,return true;
LLVM,RISCV,3444,}
LLVM,RISCV,3445,
LLVM,RISCV,3446,case VK_<ISA_LIT>_PLT : return <STR_LIT> ;
LLVM,RISCV,3447,case VK_<ISA_LIT>_PCREL_HI : return true;
LLVM,RISCV,3448,return true;
LLVM,RISCV,3449,return llvm :: FK_InlineKind ;
LLVM,RISCV,3450,return nullptr;
LLVM,RISCV,3451,
LLVM,RISCV,3452,"return MCExpr(Kind, Expr);"
LLVM,RISCV,3453,"if ( ! getSubExpr ( ) -> evaluateAsRelocatable ( Value , nullptr , nullptr ) ) return false ;"
LLVM,RISCV,3454,
LLVM,RISCV,3455,"return new ( Ctx ) <ISA_LIT>MCExpr ( Kind , Expr ) ;"
LLVM,RISCV,3456,case VK_<ISA_LIT>_TPLT_HI21 : break ;
LLVM,RISCV,3457,}
LLVM,RISCV,3458,
LLVM,RISCV,3459,
LLVM,RISCV,3460,
LLVM,RISCV,3461,if (Expr) {
LLVM,RISCV,3462,case VK_<ISA_LIT>_PCREL_HI20 : OS << <STR_LIT> ;
LLVM,RISCV,3463,
LLVM,RISCV,3464,"if (Res.isAbsolute()) return Fixup->relocateOne(Value, Layout);"
LLVM,RISCV,3465,
LLVM,RISCV,3466,}
LLVM,RISCV,3467,
LLVM,RISCV,3468,Going back to line   auto & RAB = static_cast < <ISA_LIT>AsmBackend & > ( Layout -> getAssembler ( ) . getBackend ( ) );
LLVM,RISCV,3469,return true;
LLVM,RISCV,3470,Res = evaluateAsString ( Value.getConstant() );
LLVM,RISCV,3471,
LLVM,RISCV,3472,the layout and fixup information.
LLVM,RISCV,3473,
LLVM,RISCV,3474,
LLVM,RISCV,3475,
LLVM,RISCV,3476,
LLVM,RISCV,3477,
LLVM,RISCV,3478,
LLVM,RISCV,3479,
LLVM,RISCV,3480,
LLVM,RISCV,3481,<STR_LIT> : VK_<ISA_LIT>_Invalid
LLVM,RISCV,3482,
LLVM,RISCV,3483,}
LLVM,RISCV,3484,return nullptr;
LLVM,RISCV,3485,
LLVM,RISCV,3486,
LLVM,RISCV,3487,return OutMI;
LLVM,RISCV,3488,}
LLVM,RISCV,3489,
LLVM,RISCV,3490,
LLVM,RISCV,3491,
LLVM,RISCV,3492,
LLVM,RISCV,3493,else {
LLVM,RISCV,3494,"case MachineOperand::MO_Register: MCOp = lowerRegisterOperand(MO, AP);"
LLVM,RISCV,3495,
LLVM,RISCV,3496,return true;
LLVM,RISCV,3497,
LLVM,RISCV,3498,if ( Num != 0 ) {
LLVM,RISCV,3499,}
LLVM,RISCV,3500,
LLVM,RISCV,3501,break ;
LLVM,RISCV,3502,case <STR_LIT>: Kind = <ISA_LIT>MCExpr::VK_<ISA_LIT>_None;
LLVM,RISCV,3503,Kind = <ISA_LIT>MCExpr :: VK_MCSymbol ;
LLVM,RISCV,3504,case <STR_LIT>: on line 6.
LLVM,RISCV,3505,default: llvm_unreachable(Invalid relocation type specified in relocation expression);
LLVM,RISCV,3506,return MCOperand::createExpr(ME)
LLVM,RISCV,3507,
LLVM,RISCV,3508,the last expression created in the if statement.
LLVM,RISCV,3509,
LLVM,RISCV,3510,MO . setTargetFlags ( TargetKind ) ;
LLVM,RISCV,3511,"Expr = MCBinaryExpr :: create ( MCBinaryExpr :: Add , Expr , OffsetExpr , Ctx ) ;"
LLVM,RISCV,3512,OutMI.addOperand(MCOp);
LLVM,RISCV,3513,}
LLVM,RISCV,3514,MCOp . setReg ( Reg ) ;
LLVM,RISCV,3515,break ;
LLVM,RISCV,3516,OutMI.addOperand(MCOp);
LLVM,RISCV,3517,
LLVM,RISCV,3518,"MCOp = lowerSymbolOperand (MO, AP.GetCPISymbol(MO.getIndex()), AP);"
LLVM,RISCV,3519,break;
LLVM,RISCV,3520,
LLVM,RISCV,3521,
LLVM,RISCV,3522,case MCSymbolRefExpr :: VK_ABS : return getAbsReloc(Kind);
LLVM,RISCV,3523,default: return getPCSRELReloc(Kind);
LLVM,RISCV,3524,
LLVM,RISCV,3525,return 0;
LLVM,RISCV,3526,default: return 0;
LLVM,RISCV,3527,closing curly brace (}
LLVM,RISCV,3528,return getGOTReloc ( Kind ) ;
LLVM,RISCV,3529,
LLVM,RISCV,3530,llvm_unreachable ( <STR_LIT> ) ;
LLVM,RISCV,3531,
LLVM,RISCV,3532,target_mach = getMachOSABI(OSABI) {
LLVM,RISCV,3533,Illegal IllegalArgumentException: missing argument
LLVM,RISCV,3534,
LLVM,RISCV,3535,"MAI->addCFIInstruction( MCCFIInstruction::createOffset( nullptr, MRI.getDwarfRegNum( <STR_LIT>, true ), <STR_LIT> ) );"
LLVM,RISCV,3536,
LLVM,RISCV,3537,return X;
LLVM,RISCV,3538,CodeModel :: Medium
LLVM,RISCV,3539,
LLVM,RISCV,3540,return X;
LLVM,RISCV,3541,
LLVM,RISCV,3542,"return createDWARFStreamer(Ctx, MAB, OS, Emitter, RelaxAll);"
LLVM,RISCV,3543,"return new MCSubtargetInfo(TT, CPU, FS);"
LLVM,RISCV,3544,"return new MCSubtargetInfo(TT, CPU, FS);"
LLVM,RISCV,3545,"TargetRegistry :: RegisterMCAsmParser ( The<ISA_LIT>Target , create<ISA_LIT>MCAsmParser ) ;"
LLVM,RISCV,3546,"return new MCSubtargetInfo(TT, CPU, FS);"
LLVM,RISCV,3547,"TargetRegistry :: RegisterMCAsmInfo(*T, create<ISA_LIT>MCAsmInfo);"
LLVM,RISCV,3548,"TargetRegistry :: RegisterMCAsmInfo ( * T , create<ISA_LIT>MCAsmInfo ) ;"
LLVM,RISCV,3549,"if ( TT . isOSBinFormatELF ( ) ) return new <ISA_LIT>TargetELFStreamer ( S , STI ) ;"
LLVM,RISCV,3550,MCTargetStreamer * Streamer = nullptr ;
LLVM,RISCV,3551,"TargetRegistry :: RegisterMCObjectStreamer ( * T , create<ISA_LIT>ELFStreamer ) ;"
LLVM,RISCV,3552,"MCCFIInstruction Inst2 = MCCFIInstruction :: createOffset ( nullptr , BP, <NUM_LIT> ) ;"
LLVM,RISCV,3553,
LLVM,RISCV,3554,
LLVM,RISCV,3555,return X ;
LLVM,RISCV,3556,X >::InitMCRegisterInfo ( TT ) ;
LLVM,RISCV,3557,"TargetRegistry :: RegisterMCSubtargetInfo ( * T , create<ISA_LIT>MCSubtargetInfo ) ;"
LLVM,RISCV,3558,}
LLVM,RISCV,3559,CPUName = TT.isArch64Bit() ? <STR_LIT> : <STR_LIT>
LLVM,RISCV,3560,std::cout << The CPU name is  << CPUName << std::endl;
LLVM,RISCV,3561,return TT.isArch64Bit() ? <STR_LIT> : <STR_LIT>
LLVM,RISCV,3562,
LLVM,RISCV,3563,"MAI->addFrameOffsetRegister(SP, 0);"
LLVM,RISCV,3564,"Register LB = MRI . getDwarfRegNum ( <EXPR_LIT> , false ) ;"
LLVM,RISCV,3565,return nullptr;
LLVM,RISCV,3566,
LLVM,RISCV,3567,MAI->addInitialFrameState(Inst);
LLVM,RISCV,3568,MAI->initMCAsmInfo(Options);
LLVM,RISCV,3569,"MOFI->emitInstruction(Ctx, PIC, LargeCodeModel) ;"
LLVM,RISCV,3570,MOFI->setIsLittleEndian(true);
LLVM,RISCV,3571,
LLVM,RISCV,3572,
LLVM,RISCV,3573,
LLVM,RISCV,3574,Target = Addr + Inst.getOperand(<NUM_LIT>).getImm();
LLVM,RISCV,3575,"TargetRegistry :: RegisterELFObjectWriter ( * T , create<ISA_LIT>ELFObjectWriter ) ;"
LLVM,RISCV,3576,"TargetRegistry :: RegisterMCTargetOptions ( * T , create<ISA_LIT>MCTargetOptions ) ;"
LLVM,RISCV,3577,
LLVM,RISCV,3578,
LLVM,RISCV,3579,"TargetRegistry :: RegisterMCCodeGenInfo ( * T , create<ISA_LIT>MCCodeGenInfo ) ;"
LLVM,RISCV,3580,"MCCFIInstruction Inst2 = MCCFIInstruction::cfiDefCfaOffset(nullptr, SP, <NUM_LIT>);"
LLVM,RISCV,3581,RAReg = <STR_LIT> ;
LLVM,RISCV,3582,"TargetRegistry :: RegisterMCAsmParser ( * T , create<ISA_LIT>MCParser ) ;"
LLVM,RISCV,3583,}
LLVM,RISCV,3584,"TargetRegistry::RegisterMCAsmParser(*T, create<ISA_LIT>MCAsmParser);"
LLVM,RISCV,3585,}
LLVM,RISCV,3586,"TargetRegistry :: RegisterTarget ( The<ISA_LIT>Target , create<ISA_LIT>Target ) ;"
LLVM,RISCV,3587,return MAI;
LLVM,RISCV,3588,"TargetRegistry :: RegisterAsmTargetStreamer ( * T , create<ISA_LIT>AsmTargetStreamer ) ;"
LLVM,RISCV,3589,
LLVM,RISCV,3590,}
LLVM,RISCV,3591,
LLVM,RISCV,3592,
LLVM,RISCV,3593,}
LLVM,RISCV,3594,"JSelUEACompilePlugin ( X , {"
LLVM,RISCV,3595,
LLVM,RISCV,3596,"if (TT.isOSBinFormatMachO()) return new <ISA_LIT>TargetMachOStreamer(S, STI);"
LLVM,RISCV,3597,"TargetRegistry :: RegisterMCCodeEmitter ( * T , create<ISA_LIT>CodeEmitter ) ;"
LLVM,RISCV,3598,
LLVM,RISCV,3599,
LLVM,RISCV,3600,
LLVM,RISCV,3601,
LLVM,RISCV,3602,return true;
LLVM,RISCV,3603,ImmOp . setOffset ( Offset ) ;
LLVM,RISCV,3604,}
LLVM,RISCV,3605,
LLVM,RISCV,3606,if ( HiLUI . isInstruction ( HiLUI ) ) {
LLVM,RISCV,3607,
LLVM,RISCV,3608,
LLVM,RISCV,3609,Tail.getOperand(1).setOffset(Offset);
LLVM,RISCV,3610,return true ;
LLVM,RISCV,3611,if ( ! isInt < <NUM_LIT> > ( Offset ) ) return false ;
LLVM,RISCV,3612,if (HiLUI.getOpcode() == MachineInstr::LUI) {
LLVM,RISCV,3613,}
LLVM,RISCV,3614,
LLVM,RISCV,3615,return true ;
LLVM,RISCV,3616,
LLVM,RISCV,3617,
LLVM,RISCV,3618,LoADDI.addOperand(ImmOp);
LLVM,RISCV,3619,a return true;
LLVM,RISCV,3620,return true;
LLVM,RISCV,3621,
LLVM,RISCV,3622,}
LLVM,RISCV,3623,
LLVM,RISCV,3624,
LLVM,RISCV,3625,
LLVM,RISCV,3626,
LLVM,RISCV,3627,
LLVM,RISCV,3628,}
LLVM,RISCV,3629,}
LLVM,RISCV,3630,}
LLVM,RISCV,3631,}
LLVM,RISCV,3632,
LLVM,RISCV,3633,return modified;
LLVM,RISCV,3634,}
LLVM,RISCV,3635,
LLVM,RISCV,3636,
LLVM,RISCV,3637,Setups.push_back(LoopSetup) ;
LLVM,RISCV,3638,AU.addPreserved<MachineDominatorTree>();
LLVM,RISCV,3639,MachineFunctionPass :: doInitialization(M) ;
LLVM,RISCV,3640,
LLVM,RISCV,3641,}
LLVM,RISCV,3642,
LLVM,RISCV,3643,
LLVM,RISCV,3644,
LLVM,RISCV,3645,FunctionPass * llvm::createISA_LIT RedundantCopyEliminationPass ( ) {
LLVM,RISCV,3646,
LLVM,RISCV,3647,
LLVM,RISCV,3648,
LLVM,RISCV,3649,
LLVM,RISCV,3650,
LLVM,RISCV,3651,
LLVM,RISCV,3652,"if (MI->modifiesRegister(TargetReg, TRI)) break;"
LLVM,RISCV,3653,
LLVM,RISCV,3654,return Changed ;
LLVM,RISCV,3655,RAI.TargetRegisterInfo = TRI;
LLVM,RISCV,3656,
LLVM,RISCV,3657,return TRI.getNumRegs();
LLVM,RISCV,3658,
LLVM,RISCV,3659,
LLVM,RISCV,3660,
LLVM,RISCV,3661,}
LLVM,RISCV,3662,report_fatal_error(<STR_LIT>);
LLVM,RISCV,3663,return CSR_ILP32D_LP64D_SaveList;
LLVM,RISCV,3664,
LLVM,RISCV,3665,break;
LLVM,RISCV,3666,}
LLVM,RISCV,3667,
LLVM,RISCV,3668,
LLVM,RISCV,3669,*}
LLVM,RISCV,3670,"BuildMI (MBB, II, DL, TII->get(ZvlssegInfo.SpillOpcode), MI.getOperand(FIOperandNum + ZvlssegInfo.SpillOffset).getReg()).addReg(MI.getOperand(FIOperandNum).getReg(), getKillRegState(MI.getOperand(FIOperandNum).isKill())).addReg(MI.getOperand(FIOperandNum + ZvlssegInfo.InsOffset).getReg(), ZvlssegInfo.InsFlags);"
LLVM,RISCV,3671,
LLVM,RISCV,3672,
LLVM,RISCV,3673,Ops.push_back(dwarf::DW_OP_deref);
LLVM,RISCV,3674,Ops . append ( {
LLVM,RISCV,3675,
LLVM,RISCV,3676,
LLVM,RISCV,3677,
LLVM,RISCV,3678,"if ( TargetFrameIndexInfo -> hasVA ( MF ) ) markSuperRegs ( Reserved , <STR_LIT> ) ;"
LLVM,RISCV,3679,
LLVM,RISCV,3680,}
LLVM,RISCV,3681,
LLVM,RISCV,3682,
LLVM,RISCV,3683,
LLVM,RISCV,3684,"next statement MachineInstr * MI = BuildMI(MBB, II, DL, TII->get(<STR_LIT>)) .addReg(FrameReg) .addImm(Offset) .addReg(<STR_LIT>);"
LLVM,RISCV,3685,}
LLVM,RISCV,3686,
LLVM,RISCV,3687,Insert a new condition:
LLVM,RISCV,3688,"ADDIWimm (  DestReg ,  FI , Offset . getFixed ( ) , MBB , II , DL , TII , STM ,   MI . getOpcode ( ) , STI ) ;"
LLVM,RISCV,3689,return CSR_XLEN_ILP32_LP64_SaveList;
LLVM,RISCV,3690,case <STR_LIT> : return CSR_IL32PC64D_L64PC128D_RegMask ;
LLVM,RISCV,3691,
LLVM,RISCV,3692,
LLVM,RISCV,3693,
LLVM,RISCV,3694,return GenRegisterInfo;
LLVM,RISCV,3695,return false ;
LLVM,RISCV,3696,auto * MFInfo = RVFI->getMachineFunctionInfo();
LLVM,RISCV,3697,assert(isInt<<<NUM_LIT>>>(Offset) && <STR_LIT>);
LLVM,RISCV,3698,}
LLVM,RISCV,3699,auto FII = FixedCSRFIMap . find ( Reg );
LLVM,RISCV,3700,if (FrameIdx == 0) {
LLVM,RISCV,3701,assert(isInt<32767>(Offset) && Offset must fit in 16 bits.);
LLVM,RISCV,3702,
LLVM,RISCV,3703,
LLVM,RISCV,3704,
LLVM,RISCV,3705,assert ( checkAllSuperRegsMarked ( Reserved ) ) ;
LLVM,RISCV,3706,if ( FII->second != nullptr) return true;
LLVM,RISCV,3707,if (FII == FixedCSRFIMap.end()) return false;
LLVM,RISCV,3708,return false;
LLVM,RISCV,3709,
LLVM,RISCV,3710,
LLVM,RISCV,3711,}
LLVM,RISCV,3712,
LLVM,RISCV,3713,
LLVM,RISCV,3714,case LP64F:
LLVM,RISCV,3715,"TFI->emitPrologue(MF, MI);"
LLVM,RISCV,3716,MI.getOperand(FIOperandNum).ChangeToFrameIndex(FrameIndex);
LLVM,RISCV,3717,
LLVM,RISCV,3718,
LLVM,RISCV,3719,return Reserved;
LLVM,RISCV,3720,
LLVM,RISCV,3721,
LLVM,RISCV,3722,"Debug(FrameReg = %d, Offset = %lld, IsKill = %d, FrameReg, Offset, IsKill);"
LLVM,RISCV,3723,FrameIndex = MF.getFrameInfo()->getObjectOffset(...) + FrameReg;
LLVM,RISCV,3724,int Reg = MRI.removeRegFromLiveOut(MI.getParent().getParent());
LLVM,RISCV,3725,
LLVM,RISCV,3726,return CSR_RV64F_SaveList ;
LLVM,RISCV,3727,
LLVM,RISCV,3728,
LLVM,RISCV,3729,Reserved.set(<STR_LIT>);
LLVM,RISCV,3730,
LLVM,RISCV,3731,
LLVM,RISCV,3732,
LLVM,RISCV,3733,MF.addLiveIn ( Register );
LLVM,RISCV,3734,
LLVM,RISCV,3735,
LLVM,RISCV,3736,
LLVM,RISCV,3737,
LLVM,RISCV,3738,return CSR_RID + N ;
LLVM,RISCV,3739,}
LLVM,RISCV,3740,}
LLVM,RISCV,3741,
LLVM,RISCV,3742,
LLVM,RISCV,3743,
LLVM,RISCV,3744,}
LLVM,RISCV,3745,
LLVM,RISCV,3746,
LLVM,RISCV,3747,
LLVM,RISCV,3748,}
LLVM,RISCV,3749,}
LLVM,RISCV,3750,<p> lastVSETVLIOfMBB[MBB] = tailVSETVLI[MBB];
LLVM,RISCV,3751,}
LLVM,RISCV,3752,
LLVM,RISCV,3753,
LLVM,RISCV,3754,if (MBB.empty()) {
LLVM,RISCV,3755,{
LLVM,RISCV,3756,}
LLVM,RISCV,3757,
LLVM,RISCV,3758,
LLVM,RISCV,3759,
LLVM,RISCV,3760,
LLVM,RISCV,3761,}
LLVM,RISCV,3762,else if ( redundancyVSETVLI . size ( ) == 1 ) return true ;
LLVM,RISCV,3763,MF = restructureMF(MF);
LLVM,RISCV,3764,if (getTargetMachine().getSubtarget<VSETVLSubtarget>().getFeatureBits().count(VSETVFL)) {
LLVM,RISCV,3765,
LLVM,RISCV,3766,
LLVM,RISCV,3767,
LLVM,RISCV,3768,
LLVM,RISCV,3769,}
LLVM,RISCV,3770,
LLVM,RISCV,3771,return;
LLVM,RISCV,3772,throw new Metadata_Exception(Metadata type cannot be uninitialized.);
LLVM,RISCV,3773,return false;
LLVM,RISCV,3774,return false;
LLVM,RISCV,3775,}
LLVM,RISCV,3776,unsigned int value ;
LLVM,RISCV,3777,
LLVM,RISCV,3778,}
LLVM,RISCV,3779,
LLVM,RISCV,3780,Args . push_back ( Entry ) ;
LLVM,RISCV,3781,
LLVM,RISCV,3782,
LLVM,RISCV,3783,
LLVM,RISCV,3784,return reinterpret_cast<const <ISA_LIT>Subtarget&>(DAG.getSubtarget());
LLVM,RISCV,3785,n_subtarget = <ISA_LIT> :: <ISA_LIT>Subtarget::create ( DAG );
LLVM,RISCV,3786,return;
LLVM,RISCV,3787,
LLVM,RISCV,3788,Worklist . push_back ( UserOp . getParent ( ) );
LLVM,RISCV,3789,a break;
LLVM,RISCV,3790,
LLVM,RISCV,3791,
LLVM,RISCV,3792,return false;
LLVM,RISCV,3793,}
LLVM,RISCV,3794,return true ;
LLVM,RISCV,3795,
LLVM,RISCV,3796,return new <ISA_LIT>PtrToInt ( ) ;
LLVM,RISCV,3797,}
LLVM,RISCV,3798,return passName;
LLVM,RISCV,3799,
LLVM,RISCV,3800,}
LLVM,RISCV,3801,
LLVM,RISCV,3802,return llvm::createSExtWRemovalPass(ID);
LLVM,RISCV,3803,}
LLVM,RISCV,3804,LLVM_DEBUG(dbgs() << Constrained register class mismatch);
LLVM,RISCV,3805,Reloc::Model return RM;
LLVM,RISCV,3806,
LLVM,RISCV,3807,}
LLVM,RISCV,3808,
LLVM,RISCV,3809,return nullptr;
LLVM,RISCV,3810,
LLVM,RISCV,3811,
LLVM,RISCV,3812,
LLVM,RISCV,3813,return CM != CodeModel :: KC
LLVM,RISCV,3814,
LLVM,RISCV,3815,Possible:
LLVM,RISCV,3816,
LLVM,RISCV,3817,
LLVM,RISCV,3818,}
LLVM,RISCV,3819,
LLVM,RISCV,3820,
LLVM,RISCV,3821,
LLVM,RISCV,3822,
LLVM,RISCV,3823,return EnableAutoSave;
LLVM,RISCV,3824,
LLVM,RISCV,3825,return (enableUnalignedScalarMem);
LLVM,RISCV,3826,
LLVM,RISCV,3827,
LLVM,RISCV,3828,
LLVM,RISCV,3829,return llvm::MaxInterleaveFactor ;
LLVM,RISCV,3830,}
LLVM,RISCV,3831,
LLVM,RISCV,3832,}
LLVM,RISCV,3833,
LLVM,RISCV,3834,
LLVM,RISCV,3835,for ( unsigned loop = 2 ;
LLVM,RISCV,3836,
LLVM,RISCV,3837,
LLVM,RISCV,3838,}
LLVM,RISCV,3839,}
LLVM,RISCV,3840,}
LLVM,RISCV,3841,1. abstract{
LLVM,RISCV,3842,
LLVM,RISCV,3843,
LLVM,RISCV,3844,
LLVM,RISCV,3845,
LLVM,RISCV,3846,
LLVM,RISCV,3847,
LLVM,RISCV,3848,
LLVM,RISCV,3849,
LLVM,RISCV,3850,
LLVM,RISCV,3851,return _hasStdExtZba;
LLVM,RISCV,3852,}
LLVM,RISCV,3853,
LLVM,RISCV,3854,
LLVM,RISCV,3855,+= 1;
LLVM,RISCV,3856,roc_bool to_ret=parf2 (string)(bool);
LLVM,RISCV,3857,
LLVM,RISCV,3858,
LLVM,RISCV,3859,}
LLVM,RISCV,3860,
LLVM,RISCV,3861,
LLVM,RISCV,3862,}
LLVM,RISCV,3863,
LLVM,RISCV,3864,
LLVM,RISCV,3865,}
LLVM,RISCV,3866,
LLVM,RISCV,3867,
LLVM,RISCV,3868,
LLVM,RISCV,3869,
LLVM,RISCV,3870,}
LLVM,RISCV,3871,
LLVM,RISCV,3872,}
LLVM,RISCV,3873,return true;
LLVM,RISCV,3874,return true;
LLVM,RISCV,3875,}
LLVM,RISCV,3876,
LLVM,RISCV,3877,<\s> if (this.variable != null) {
LLVM,RISCV,3878,
LLVM,RISCV,3879,Either an opening curly brace ({
LLVM,RISCV,3880,return true;
LLVM,RISCV,3881,
LLVM,RISCV,3882,
LLVM,RISCV,3883,return false;
LLVM,RISCV,3884,
LLVM,RISCV,3885,}
LLVM,RISCV,3886,return !std::is_const_v<typename accessor<std::remove_const_t<T>>::value_type>;
LLVM,RISCV,3887,
LLVM,RISCV,3888,
LLVM,RISCV,3889,
LLVM,RISCV,3890,}
LLVM,RISCV,3891,
LLVM,RISCV,3892,
LLVM,RISCV,3893,
LLVM,RISCV,3894,: bool is64 = is64Bit();
LLVM,RISCV,3895,}
LLVM,RISCV,3896,
LLVM,RISCV,3897,
LLVM,RISCV,3898,
LLVM,RISCV,3899,return this->arch == RV32E;
LLVM,RISCV,3900,assert ( hasVInstructions ( ) && <STR_LIT> ) ;
LLVM,RISCV,3901,
LLVM,RISCV,3902,
LLVM,RISCV,3903,
LLVM,RISCV,3904,}
LLVM,RISCV,3905,}
LLVM,RISCV,3906,"return Is64Bit ? SubtargetFeatures & Subtarget::getDefaultFeatures(CPU, FS) : SubtargetFeatures & Subtarget::GetMistunedFeatures (TuneCPU, FS);"
LLVM,RISCV,3907,
LLVM,RISCV,3908,return <ISA_LIT>_ANDRIOD3 ;
LLVM,RISCV,3909,}
LLVM,RISCV,3910,
LLVM,RISCV,3911,}
LLVM,RISCV,3912,
LLVM,RISCV,3913,return RVVVectorBitsMax;
LLVM,RISCV,3914,
LLVM,RISCV,3915,
LLVM,RISCV,3916,cout << Standard extensions version is valid.;
LLVM,RISCV,3917,
LLVM,RISCV,3918,
LLVM,RISCV,3919,
LLVM,RISCV,3920,
LLVM,RISCV,3921,"<STR_LIT> ( TT , getRegisterInfo ( ) ) ;"
LLVM,RISCV,3922,
LLVM,RISCV,3923,
LLVM,RISCV,3924,
LLVM,RISCV,3925,
LLVM,RISCV,3926,
LLVM,RISCV,3927,return ELEN;
LLVM,RISCV,3928,}
LLVM,RISCV,3929,
LLVM,RISCV,3930,
LLVM,RISCV,3931,
LLVM,RISCV,3932,
LLVM,RISCV,3933,
LLVM,RISCV,3934,
LLVM,RISCV,3935,
LLVM,RISCV,3936,
LLVM,RISCV,3937,if (window()->modal()) {
LLVM,RISCV,3938,RegBankInfo->reset(RBI);
LLVM,RISCV,3939,
LLVM,RISCV,3940,
LLVM,RISCV,3941,
LLVM,RISCV,3942,FS.enableJOINT_DWARF;
LLVM,RISCV,3943,
LLVM,RISCV,3944,
LLVM,RISCV,3945,std::string HWMode = getHwMode();
LLVM,RISCV,3946,
LLVM,RISCV,3947,
LLVM,RISCV,3948,
LLVM,RISCV,3949,
LLVM,RISCV,3950,assert ( isPowerOf2_32 ( RVVVectorBitsMax ) && <STR_LIT> );
LLVM,RISCV,3951,assert (Min < RVVVectorBitsMax);
LLVM,RISCV,3952,
LLVM,RISCV,3953,
LLVM,RISCV,3954,return HasStdExtZve64x;
LLVM,RISCV,3955,
LLVM,RISCV,3956,
LLVM,RISCV,3957,
LLVM,RISCV,3958,
LLVM,RISCV,3959,return is64Bit();
LLVM,RISCV,3960,
LLVM,RISCV,3961,
LLVM,RISCV,3962,
LLVM,RISCV,3963,Debug.Log(Extension X Core Version Found.);
LLVM,RISCV,3964,}
LLVM,RISCV,3965,}
LLVM,RISCV,3966,}
LLVM,RISCV,3967,}
LLVM,RISCV,3968,
LLVM,RISCV,3969,
LLVM,RISCV,3970,return HasStdExtV2 && hasStdExtD2 ( ) ;
LLVM,RISCV,3971,`bool F64Instructions = hasF64Instructions();
LLVM,RISCV,3972,
LLVM,RISCV,3973,
LLVM,RISCV,3974,RegBankInfo.reset(RBI);
LLVM,RISCV,3975,assert ( RVVVectorBitsMax <= RVVVectorBitsMin || RVVVectorBitsMax == (RVVVectorBitsMax & -RVVVectorBitsMax));
LLVM,RISCV,3976,"Min = std :: min ( RVVVectorBitsMin , RVVVectorBitsMax ) ;"
LLVM,RISCV,3977,{
LLVM,RISCV,3978,
LLVM,RISCV,3979,
LLVM,RISCV,3980,
LLVM,RISCV,3981,
LLVM,RISCV,3982,
LLVM,RISCV,3983,
LLVM,RISCV,3984,
LLVM,RISCV,3985,
LLVM,RISCV,3986,
LLVM,RISCV,3987,
LLVM,RISCV,3988,return PowerOf2Floor ( ( Max < 8 || Max > 8192 ) ? 8 : Max ) ;
LLVM,RISCV,3989,
LLVM,RISCV,3990,
LLVM,RISCV,3991,
LLVM,RISCV,3992,if (HasAVX && HasFMA) {
LLVM,RISCV,3993,
LLVM,RISCV,3994,Pattern: The next statement should start with auto * NF = new <ISA_LIT>NodeFactory;
LLVM,RISCV,3995,
LLVM,RISCV,3996,return The<ISA_LIT>32Target ;
LLVM,RISCV,3997,
LLVM,RISCV,3998,return The<ISA_LIT>64Target ;
LLVM,RISCV,3999,
LLVM,RISCV,4000,<Target>The<ISA_LIT>32Target.nextStatement();
LLVM,RISCV,4001,return &The<ISA_LIT>32Target ;
LLVM,RISCV,4002,
LLVM,RISCV,4003,
LLVM,RISCV,4004,return X;
LLVM,RISCV,4005,"virtual void adjustTargetOptions(const llvm::CodeGen::CodeGenOptions &Opts, llvm::TargetOptions &TargetOpts) }"
LLVM,RISCV,4006,std::string Result = Ret + (TT.isArchBigEndian() ? <SOME_STR> : <SOME_OTHER_STR>);
LLVM,RISCV,4007,
LLVM,RISCV,4008,
LLVM,RISCV,4009,
LLVM,RISCV,4010,
LLVM,RISCV,4011,"likely define the constructor for the <ISA_LIT>64TargetMachine, which"
LLVM,RISCV,4012,
LLVM,RISCV,4013,"ISA_LIT> addPass( <ISA_LIT>CreatePrintMachineInstructionPass(raw_ostream &Out, const std::string &Banner) );"
LLVM,RISCV,4014,}
LLVM,RISCV,4015,
LLVM,RISCV,4016,"a return statement that creates a new instance of the yaml::MachineFunctionInfo class, passing in the copy of the MFI object as an argument."
LLVM,RISCV,4017,return MFI->getTargetMachine();
LLVM,RISCV,4018,return TargetTransformInfo(F.getParent()->getDataLayout());
LLVM,RISCV,4019,
LLVM,RISCV,4020,
LLVM,RISCV,4021,
LLVM,RISCV,4022,
LLVM,RISCV,4023,PassConfig *conf = new TargetPassConfig(PM);
LLVM,RISCV,4024,}
LLVM,RISCV,4025,return CodeModel::Small.
LLVM,RISCV,4026,Else return null ;
LLVM,RISCV,4027,
LLVM,RISCV,4028,
LLVM,RISCV,4029,"Subtarget.initializeSubtargetDependencies(TT, CPU, FS);"
LLVM,RISCV,4030,
LLVM,RISCV,4031,return <STR_LIT> ;
LLVM,RISCV,4032,return <STR_LIT> ;
LLVM,RISCV,4033,return TLOF;
LLVM,RISCV,4034,
LLVM,RISCV,4035,throw new Exception(Missing return statement after call to addGlobalInstructionSelect().);
LLVM,RISCV,4036,
LLVM,RISCV,4037,
LLVM,RISCV,4038,}
LLVM,RISCV,4039,}
LLVM,RISCV,4040,initialize<ISA_LIT>NarrowerToWidePass ( * PR ) ;
LLVM,RISCV,4041,return true;
LLVM,RISCV,4042,
LLVM,RISCV,4043,
LLVM,RISCV,4044,"X.addPass(create<ISA_LIT>ISelDag(), false);"
LLVM,RISCV,4045,
LLVM,RISCV,4046,
LLVM,RISCV,4047,throw new Error(Unknown optimization level);
LLVM,RISCV,4048,addPass ( create<ISA_LIT>CFLAndersAAWrapperPass ( ) ) ;
LLVM,RISCV,4049,return false;
LLVM,RISCV,4050,
LLVM,RISCV,4051,return false;
LLVM,RISCV,4052,the closing curly brace ('}
LLVM,RISCV,4053,
LLVM,RISCV,4054,}
LLVM,RISCV,4055,
LLVM,RISCV,4056,addPass ( create<ISA_SRCPROTO>ExpandAtomicPseudoPass ( ) ) ;
LLVM,RISCV,4057,}
LLVM,RISCV,4058,"If no statement follows, the next statement is }"
LLVM,RISCV,4059,return;
LLVM,RISCV,4060,std::vector<MachineOperand> VariantDatas = MI.getOperand(UXI).getVariantDatas();
LLVM,RISCV,4061,return true ;
LLVM,RISCV,4062,
LLVM,RISCV,4063,return  <STR_LIT> ;
LLVM,RISCV,4064,
LLVM,RISCV,4065,"I = new SubtargetInfo(CPU, TuneCPU, FS);"
LLVM,RISCV,4066,
LLVM,RISCV,4067,return <ISA_LIT>IsNoop;
LLVM,RISCV,4068,return (SrcAS == DstAS);
LLVM,RISCV,4069,initialize<ISA_LIT>GatherScatterLoweringPass ( * PR ) ;
LLVM,RISCV,4070,addPass ( create<RegisterSchedulerOptPass ( ) ) ;
LLVM,RISCV,4071,
LLVM,RISCV,4072,(}
LLVM,RISCV,4073,initialize<ISA_LIT>TgtCompressOptPass(*PR);
LLVM,RISCV,4074,
LLVM,RISCV,4075,
LLVM,RISCV,4076,addPass( create<ISA_LIT>DeadStoreEliminationPass() );
LLVM,RISCV,4077,"I->initSubtargetFeatures(CPU, FS, ABIClass);"
LLVM,RISCV,4078,initialize<ISA_LIT>LoadStoreCompressionPass ( * PR ) ;
LLVM,RISCV,4079,
LLVM,RISCV,4080,<S> addPass ( createCheriCalleeAnalysisPass ( ) ) ;
LLVM,RISCV,4081,if ( ABI != <STR_LIT> && <STR_LIT> ( ABI ) ) {
LLVM,RISCV,4082,
LLVM,RISCV,4083,return (SrcAS == DstAS);
LLVM,RISCV,4084,
LLVM,RISCV,4085,}
LLVM,RISCV,4086,initialize<ISA_LIT>LegalizeTypesPass ( * PR ) ;
LLVM,RISCV,4087,isELF ( ) const = default ;
LLVM,RISCV,4088,addPass (create<ISA_LIT>ExpandUnreachableBlockEliminationPass());
LLVM,RISCV,4089,
LLVM,RISCV,4090,return true;
LLVM,RISCV,4091,
LLVM,RISCV,4092,
LLVM,RISCV,4093,}
LLVM,RISCV,4094,
LLVM,RISCV,4095,
LLVM,RISCV,4096,
LLVM,RISCV,4097,PR->registerPass(Y) ;
LLVM,RISCV,4098,
LLVM,RISCV,4099,"If the compiler optimization level is not CodeGenOpt :: None, then add a Pass to create PulpHWLoopsPass."
LLVM,RISCV,4100,}
LLVM,RISCV,4101,
LLVM,RISCV,4102,}
LLVM,RISCV,4103,addPass ( create<ISA_LIT>ConstantPropagationPass ( ) ) ;
LLVM,RISCV,4104,
LLVM,RISCV,4105,}
LLVM,RISCV,4106,"a constructor for the 64TargetMachine class, which takes in a Target object T, Triple object TT, StringRef objects CPU and FS, TargetOptions object Options, optional Reloc::Model object RM, CodeModel::Model object CM, and CodeGenOpt::Level object OL. It calls the constructor from the parent class TargetMachine with the specified parameters."
LLVM,RISCV,4107,
LLVM,RISCV,4108,}
LLVM,RISCV,4109,
LLVM,RISCV,4110,
LLVM,RISCV,4111,
LLVM,RISCV,4112,<S> void <ISA_LIT>PassConfig :: addIRPasses ( ) {
LLVM,RISCV,4113,<ISA_LIT>MIRBuilder.init();
LLVM,RISCV,4114,}
LLVM,RISCV,4115,
LLVM,RISCV,4116,
LLVM,RISCV,4117,
LLVM,RISCV,4118,}
LLVM,RISCV,4119,
LLVM,RISCV,4120,Pass *ExpandPseudoPass = PR->getPass(ISA_LIT);
LLVM,RISCV,4121,initialize<ISA_LIT>ExpandPseudoPass(*PR);
LLVM,RISCV,4122,
LLVM,RISCV,4123,return *new CBELoweringPass();
LLVM,RISCV,4124,}
LLVM,RISCV,4125,}
LLVM,RISCV,4126,}
LLVM,RISCV,4127,}
LLVM,RISCV,4128,"DataSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ;"
LLVM,RISCV,4129,"return llvm::TargetLoweringObjectFile::Initialize(Ctx, TM);"
LLVM,RISCV,4130,
LLVM,RISCV,4131,"It is likely that the statement following this code snippet would involve a conditional or a logical operation, as the code currently includes a comparison and a logical operator. Possible next statements could include:"
LLVM,RISCV,4132,return SmallDataSection ;
LLVM,RISCV,4133,return RTM.getABIAlignment(Size);
LLVM,RISCV,4134,return nullptr;
LLVM,RISCV,4135,if (isReadOnlyData(C)) return SmallReadOnlyDataSection;
LLVM,RISCV,4136,
LLVM,RISCV,4137,
LLVM,RISCV,4138,OS << <STR_LIT> << Attribute << <STR_LIT> << Twine ( Value ) << <STR_LIT> ;
LLVM,RISCV,4139,OS << <STR_LIT> << Attribute << <STR_LIT> << Twine ( Value ) << <STR_LIT> << <END_STATEMENT>;
LLVM,RISCV,4140,TypeError: unsupported operand type(s) for <<: 'os' and 'str'
LLVM,RISCV,4141,return;
LLVM,RISCV,4142,
LLVM,RISCV,4143,
LLVM,RISCV,4144,
LLVM,RISCV,4145,
LLVM,RISCV,4146,OS >> <NUM_LIT> ;
LLVM,RISCV,4147,
LLVM,RISCV,4148,err ';
LLVM,RISCV,4149,OS << \t.option rvc\n;
LLVM,RISCV,4150,llvm::emitTarget llvm::emitTarget
LLVM,RISCV,4151,
LLVM,RISCV,4152,
LLVM,RISCV,4153,
LLVM,RISCV,4154,
LLVM,RISCV,4155,
LLVM,RISCV,4156,
LLVM,RISCV,4157,
LLVM,RISCV,4158,
LLVM,RISCV,4159,}
LLVM,RISCV,4160,
LLVM,RISCV,4161,return OS;
LLVM,RISCV,4162,}
LLVM,RISCV,4163,
LLVM,RISCV,4164,
LLVM,RISCV,4165,}
LLVM,RISCV,4166,
LLVM,RISCV,4167,}
LLVM,RISCV,4168,
LLVM,RISCV,4169,something like: if (STI.hasFeature(<STR_LIT>)) Arch += <STR_LIT>;
LLVM,RISCV,4170,
LLVM,RISCV,4171,consumeError(ParseResult.takeError());
LLVM,RISCV,4172,
LLVM,RISCV,4173,
LLVM,RISCV,4174,<if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ;
LLVM,RISCV,4175,
LLVM,RISCV,4176,
LLVM,RISCV,4177,
LLVM,RISCV,4178,
LLVM,RISCV,4179,if (PowDiff <= 0) return 1;
LLVM,RISCV,4180,return <NUM_LIT>;
LLVM,RISCV,4181,"Assuming that the condition of the if statement is true, the predicted next statement would be return BaseT::getMaskedMemoryOpCost(Opcode, Src, Alignment, AddressSpace, CostKind)."
LLVM,RISCV,4182,"return BaseT :: getMaskedMemoryOpCost ( Opcode , Src , Alignment , AddressSpace , CostKind ) ;"
LLVM,RISCV,4183,
LLVM,RISCV,4184,else return <NUM_LIT> ;
LLVM,RISCV,4185,"return BaseT::getMinMaxReductionCost(Ty, CondTy, IsUnsigned, CostKind)."
LLVM,RISCV,4186,
LLVM,RISCV,4187,
LLVM,RISCV,4188,return <STR_LIT>TTI::ARVRegisterUsage ;
LLVM,RISCV,4189,if (Kind == TTI::SK_Broadcast && isa<ScalableVectorType>(Tp)) return LT.first * <NUM_LIT>
LLVM,RISCV,4190,"If Kind is equal to TTI :: SK_Broadcast and Tp is a scalable vector type, return the product of LT.first and <NUM_LIT>."
LLVM,RISCV,4191,
LLVM,RISCV,4192,return LT.first * Index + Cost;
LLVM,RISCV,4193,UP.Partial = true;
LLVM,RISCV,4194,return (DataType != nullptr && Alignment > 0);
LLVM,RISCV,4195,"Have it return isLegalMaskedScatter ( DataType , Alignment ) ;"
LLVM,RISCV,4196,
LLVM,RISCV,4197,
LLVM,RISCV,4198,
LLVM,RISCV,4199,
LLVM,RISCV,4200,if (ST->getMaxRVVVectorSizeInBits() < <NUM_LIT>) return false;
LLVM,RISCV,4201,
LLVM,RISCV,4202,return true;
LLVM,RISCV,4203,
LLVM,RISCV,4204,
LLVM,RISCV,4205,
LLVM,RISCV,4206,return TTI::TCC_Free;
LLVM,RISCV,4207,return true;
LLVM,RISCV,4208,if (isa <FixedVectorType> (DataType) && DataType->getNumElements() > ST->getMaxRVVVectorSizeInElements()) return false;
LLVM,RISCV,4209,return true;
LLVM,RISCV,4210,return TTI::TCC_Basic
LLVM,RISCV,4211,std::cout << DL.getStringRepresentation() << std::endl;
LLVM,RISCV,4212,
LLVM,RISCV,4213,
LLVM,RISCV,4214,<p>return false;
LLVM,RISCV,4215,
LLVM,RISCV,4216,
LLVM,RISCV,4217,return false;
LLVM,RISCV,4218,
LLVM,RISCV,4219,
LLVM,RISCV,4220,
LLVM,RISCV,4221,return Qfalse;
LLVM,RISCV,4222,
LLVM,RISCV,4223,return ST -> getMaxRVVVectorSizeInBits ( ) ;
LLVM,RISCV,4224,
LLVM,RISCV,4225,
LLVM,RISCV,4226,}
LLVM,RISCV,4227,if (UP.UpperBound) {
LLVM,RISCV,4228,}
LLVM,RISCV,4229,TypeSize::getFixed(ST->hasVInstructions() ? ST->getMinRVVVectorSizeInBits() : <NUM_LIT>);
LLVM,RISCV,4230,
LLVM,RISCV,4231,return TTI::TCC_Basic;
LLVM,RISCV,4232,ImmArgIdx = <NUM_LIT + 1>;
LLVM,RISCV,4233,return TTI :: TCC_Basic ;
LLVM,RISCV,4234,}
LLVM,RISCV,4235,}
LLVM,RISCV,4236,
LLVM,RISCV,4237,return false;
LLVM,RISCV,4238,}
LLVM,RISCV,4239,"return getIntImmCost(Imm, Ty);"
LLVM,RISCV,4240,
LLVM,RISCV,4241,
LLVM,RISCV,4242,
LLVM,RISCV,4243,UP.Partial = true;
LLVM,RISCV,4244,
LLVM,RISCV,4245,
LLVM,RISCV,4246,(}
LLVM,RISCV,4247,"return BaseT :: getMinMaxReductionCost ( Ty , CondTy , IsUnsigned , CostKind ) ;"
LLVM,RISCV,4248,
LLVM,RISCV,4249,
LLVM,RISCV,4250,return TypeSize :: getFixed ( ST -> getXLen ( ) ) ;
LLVM,RISCV,4251,if (isa <FixedVectorType> (DataType) && ST -> getMinRVVVectorSizeInBits ( ) == <NUM_LIT> + 1) return false;
LLVM,RISCV,4252,return true;
LLVM,RISCV,4253,
LLVM,RISCV,4254,case RecurKind :: Mul:
LLVM,RISCV,4255,return TTI::TCC_Free;
LLVM,RISCV,4256,
LLVM,RISCV,4257,
LLVM,RISCV,4258,if ( isa < FixedVectorType > ( DataType ) && DataType -> getScalarSizeInBits ( ) <= ST -> getELEN ( ) ) return true ;
LLVM,RISCV,4259,Prediction: return true;
LLVM,RISCV,4260,return false ;
LLVM,RISCV,4261,
LLVM,RISCV,4262,"return BaseT::getGatherScatterOpCost(Opcode, DataTy, Ptr, VariableMask, Alignment, CostKind, I) if the FixedVectorType is not a fixed vector type."
LLVM,RISCV,4263,
LLVM,RISCV,4264,{
LLVM,RISCV,4265,return BaseT::getMaxVScale();
LLVM,RISCV,4266,3.  return true;
LLVM,RISCV,4267,support_kinds Result = PSK_FastHardware;
LLVM,RISCV,4268,return *ST;
LLVM,RISCV,4269,}
LLVM,RISCV,4270,
LLVM,RISCV,4271,
LLVM,RISCV,4272,
LLVM,RISCV,4273,default: return false;
LLVM,ARC,0,ISA_LITAsmPrinter *AP = new <ISA_LIT>AsmPrinter(getThe<ISA_LIT>Target());
LLVM,ARC,1,
LLVM,ARC,2,
LLVM,ARC,3,
LLVM,ARC,4,return targetStreamer;
LLVM,ARC,5,return false;
LLVM,ARC,6,
LLVM,ARC,7,
LLVM,ARC,8,return O.str();
LLVM,ARC,9,
LLVM,ARC,10,
LLVM,ARC,11,
LLVM,ARC,12,}
LLVM,ARC,13,}
LLVM,ARC,14,"BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), TII->get(getBRccForPseudo(MI))).addMBB(MI->getOperand(<NUM_LIT>).getMBB()).addReg(MI->getOperand(<NUM_LIT>).getReg()).add(MI->getOperand(<NUM_LIT>)).addImm(getCCForBRcc(MI->getOperand(<NUM_LIT>).getImm())).eraseFromParent();"
LLVM,ARC,15,}
LLVM,ARC,16,
LLVM,ARC,17,DEBUG(dbgs() << 'Branch instruction detected.' << '\n');
LLVM,ARC,18,}
LLVM,ARC,19,
LLVM,ARC,20,}
LLVM,ARC,21,}
LLVM,ARC,22,
LLVM,ARC,23,
LLVM,ARC,24,
LLVM,ARC,25,MI -> eraseFromParent ();
LLVM,ARC,26,
LLVM,ARC,27,
LLVM,ARC,28,Branches .push_back ( & MI . getName ( ) ) ;
LLVM,ARC,29,
LLVM,ARC,30,
LLVM,ARC,31,return MCDisassembler::Success.
LLVM,ARC,32,static_cast<int> (InsnS) : -<NUM_LIT>) );
LLVM,ARC,33,"is defining a function called DecodeGBR32ShortRegister which takes in four parameters: a reference to an MCInst object, an unsigned integer RegNo, a 64-bit integer Address, and a constant pointer to Decoder. The function checks if the RegNo is greater than a certain value and then adds a certain value to it. Finally, the function returns the result of calling another function called DecodeGPR32RegisterClass with the updated RegNo as a parameter."
LLVM,ARC,34,
LLVM,ARC,35,}
LLVM,ARC,36,
LLVM,ARC,37,LLVM_DEBUG( dbgs () << <STR_LIT> );
LLVM,ARC,38,
LLVM,ARC,39,Inst.addOperand(MCOperand::createImm(SignExtend32 <<NUM_LIT>>(S9)));
LLVM,ARC,40,
LLVM,ARC,41,}
LLVM,ARC,42,
LLVM,ARC,43,
LLVM,ARC,44,return (nullptr != Disassembler);
LLVM,ARC,45,
LLVM,ARC,46,
LLVM,ARC,47,
LLVM,ARC,48,LLVM_DEBUG(dbgs() << No matching instruction table for this decoder!\n);
LLVM,ARC,49,"Result = decodeInstruction ( DecoderTable48 , Instr , Insn48 , Address , this , STI ) ;"
LLVM,ARC,50,
LLVM,ARC,51,return MCDisassembler :: Success;
LLVM,ARC,52,Inst.execute();
LLVM,ARC,53,
LLVM,ARC,54,Inst.addOperand (MCOperand::createImm (Result));
LLVM,ARC,55,"Field U7 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ;"
LLVM,ARC,56,return the value of MCDisassembler::Success.
LLVM,ARC,57,{
LLVM,ARC,58,
LLVM,ARC,59,
LLVM,ARC,60,std::cout << B Field decoded:  << Field << std::endl;
LLVM,ARC,61,
LLVM,ARC,62,return MCDisassembler::Fail;
LLVM,ARC,63,if (S < 0) {
LLVM,ARC,64,
LLVM,ARC,65,Inst.addOperand(MCOperand::createReg(Reg2));
LLVM,ARC,66,Inst.addOperand(MCOperand::createImm(0));
LLVM,ARC,67,
LLVM,ARC,68,Inst . addOperand ( MCOperand :: createImm ( SignExtend32 < <NUM_LIT> > ( <NUM_LIT> & InsnS12 & 0xFFFFFFFF ) ) ) ;
LLVM,ARC,69,Inst .addOperand ( MCOperand::createImm (SignExtend32 <<NUM_LIT>> (<NUM_LIT> & InsnS12))));
LLVM,ARC,70,
LLVM,ARC,71,return MCDisassembler::Success;
LLVM,ARC,72,if (SrcC != <NUM_LIT>) {
LLVM,ARC,73,Inst.addOperand(MCOperand::createImm(<NUM_LIT>));
LLVM,ARC,74,}
LLVM,ARC,75,"Result = decodeInstruction(DecoderTable32, Instr, Insn32, Address, this, STI);"
LLVM,ARC,76,Inst.addOperand(MCOperand::createReg(DstA));
LLVM,ARC,77,if ( decodeDField ( Insn ) == <NUM_LIT> ) {
LLVM,ARC,78,
LLVM,ARC,79,DIm = (Insn >> <NUM_DUMMY>) ;
LLVM,ARC,80,}
LLVM,ARC,81,
LLVM,ARC,82,
LLVM,ARC,83,}
LLVM,ARC,84,return Insn ;
LLVM,ARC,85,
LLVM,ARC,86,
LLVM,ARC,87,"DecodeNextInstruction(Inst, Address, SignExtend32<B>(InsnS), Decoder);"
LLVM,ARC,88,Inst.clear();
LLVM,ARC,89,const unsigned max = ( <NUM_LIT> << B ) - (<NUM_LIT> * 2);
LLVM,ARC,90,
LLVM,ARC,91,"decodeRegisterClass(Decoder, GBR32RegisterClassID, RegNo, Inst);"
LLVM,ARC,92,
LLVM,ARC,93,}
LLVM,ARC,94,
LLVM,ARC,95,MCInst::addOperand(MCOperand::createImm((uint32_t)(Insn >> <NUM_LIT>)));
LLVM,ARC,96,
LLVM,ARC,97,
LLVM,ARC,98,
LLVM,ARC,99,Field Combined = Lower | Upper;
LLVM,ARC,100,
LLVM,ARC,101,
LLVM,ARC,102,
LLVM,ARC,103,
LLVM,ARC,104,
LLVM,ARC,105,
LLVM,ARC,106,if (Bytes.size() < NUM_LIT) {
LLVM,ARC,107,
LLVM,ARC,108,Insn = <NUM_LIT>;
LLVM,ARC,109,Color = blue;
LLVM,ARC,110,
LLVM,ARC,111,
LLVM,ARC,112,
LLVM,ARC,113,if (Dest.getReg() == <ISA_LIT>X86::EAX) {
LLVM,ARC,114,SI . eraseFromParent ( ) ;
LLVM,ARC,115,
LLVM,ARC,116,break ;
LLVM,ARC,117,return true;
LLVM,ARC,118,
LLVM,ARC,119,
LLVM,ARC,120,
LLVM,ARC,121,Break;
LLVM,ARC,122,}
LLVM,ARC,123,
LLVM,ARC,124,return Pass Name;
LLVM,ARC,125,ptr = new Node ;
LLVM,ARC,126,
LLVM,ARC,127,
LLVM,ARC,128,
LLVM,ARC,129,}
LLVM,ARC,130,"CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(nullptr, MRI->getDwarfRegNum(Reg, true), MFI.getObjectOffset(FI)));"
LLVM,ARC,131,}
LLVM,ARC,132,
LLVM,ARC,133,return Last;
LLVM,ARC,134,
LLVM,ARC,135,
LLVM,ARC,136,if (isInt<<<NUM_LIT>>(MoveAmount))  Opc = <STR_LIT>;
LLVM,ARC,137,return MachineBasicBlock :: iterator ( MBBI ) ;
LLVM,ARC,138,
LLVM,ARC,139,"BuildMI ( MBB , MBBI , dl , TII . get ( AdjOp ) , StackPtr ) . addReg ( StackPtr ) . addImm ( AbsAmount ) ;"
LLVM,ARC,140,}
LLVM,ARC,141,
LLVM,ARC,142,Reg = Entry . getReg ( ) ;
LLVM,ARC,143,
LLVM,ARC,144,
LLVM,ARC,145,
LLVM,ARC,146,
LLVM,ARC,147,return nullptr;
LLVM,ARC,148,
LLVM,ARC,149,RS.set(<STR_LIT>);
LLVM,ARC,150,
LLVM,ARC,151,"BuildMI (MBB, MBBI, DebugLoc(), TII->get(<STR_LIT>), <STR_LIT>) .addReg(<STR_LIT>, RegState::Implicit | RegState::Undef) .addImm(StackSize - AmountAboveFunclet);"
LLVM,ARC,152,"BuildMI ( MBB , MBBI , MBB . findDebugLoc ( MBBI ) , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ). addImm ( StackSlotsUsedByFunclet ) ;"
LLVM,ARC,153,
LLVM,ARC,154,
LLVM,ARC,155,DEBUG (dbgs() << <STR_LIT> << Allocated stack object at index  << RegScavFI <<  for register class  << RC->getName() << <STR_LIT>);
LLVM,ARC,156,}
LLVM,ARC,157,
LLVM,ARC,158,
LLVM,ARC,159,
LLVM,ARC,160,
LLVM,ARC,161,
LLVM,ARC,162,
LLVM,ARC,163,
LLVM,ARC,164,
LLVM,ARC,165,"MFI.setObjectOffset(RegI->getFrameIdx(), CurOffset);"
LLVM,ARC,166,
LLVM,ARC,167,}
LLVM,ARC,168,
LLVM,ARC,169,if ( Reg . getReg ( ) < Last ) Last = Reg . getReg ( ) ;
LLVM,ARC,170,
LLVM,ARC,171,}
LLVM,ARC,172,
LLVM,ARC,173,}
LLVM,ARC,174,
LLVM,ARC,175,
LLVM,ARC,176,
LLVM,ARC,177,LLVM_DEBUG (dbgs() << <STR_LIT> << RC->getName() << <STR_LIT> ) ;
LLVM,ARC,178,}
LLVM,ARC,179,
LLVM,ARC,180,
LLVM,ARC,181,
LLVM,ARC,182,break;
LLVM,ARC,183,MI -> getOperand ( OpNum ) . getImm ( ) = 1 ;
LLVM,ARC,184,printEndMessage(O);
LLVM,ARC,185,
LLVM,ARC,186,"printOperand(MI, OpNum, O);"
LLVM,ARC,187,
LLVM,ARC,188,case <STR_LIT> : return <STR_LIT> ;
LLVM,ARC,189,
LLVM,ARC,190,case <STR_LIT> : return <STR_LIT> ;
LLVM,ARC,191,
LLVM,ARC,192,return <STR_LIT> ;
LLVM,ARC,193,}
LLVM,ARC,194,
LLVM,ARC,195,return;
LLVM,ARC,196,return <STR_LIT> Bad condition code ;
LLVM,ARC,197,return Op;
LLVM,ARC,198,
LLVM,ARC,199,OS << '+' ;
LLVM,ARC,200,}
LLVM,ARC,201,}
LLVM,ARC,202,"printImmValue(O, offset.getImm());"
LLVM,ARC,203,
LLVM,ARC,204,
LLVM,ARC,206,
LLVM,ARC,207,class <ISA_LIT>GenRegisterInfo RegInfo ;
LLVM,ARC,208,return;
LLVM,ARC,209,return false ;
LLVM,ARC,210,assert(MFI.getObjectOffset(FrameIndex) == 0);
LLVM,ARC,211,loaded to registers with equal or higher alignment);
LLVM,ARC,212,"<STR_LIT>. setMemOperandOffset(MBB, I, MMO);"
LLVM,ARC,213,
LLVM,ARC,214,MMO->getValue() = 0;
LLVM,ARC,215,"LLVM_DEBUG(dbgs() << Spilling register  << printReg(SrcReg, TRI) << to stack slot # << FrameIndex << \n);"
LLVM,ARC,216,assert ( MMO->isStore() && Expected a store machine memory operand);
LLVM,ARC,217,
LLVM,ARC,218,
LLVM,ARC,219,
LLVM,ARC,220,
LLVM,ARC,221,
LLVM,ARC,222,
LLVM,ARC,223,"BuildMI ( & MBB , dl , get ( Cond [ 1 ] . isImm ( ) ? BccOpc = <STR_LIT> : BccOpc = <STR_LIT> ) ) . addMBB ( TBB ) ;"
LLVM,ARC,224,}
LLVM,ARC,225,
LLVM,ARC,226,
LLVM,ARC,227,
LLVM,ARC,228,
LLVM,ARC,229,
LLVM,ARC,230,}
LLVM,ARC,231,MIB->addCond(FBB);
LLVM,ARC,232,else {
LLVM,ARC,233,
LLVM,ARC,234,
LLVM,ARC,235,
LLVM,ARC,236,"LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( DestReg , TRI ) << <STR_LIT> << FrameIndex + 1 << <STR_LIT> ) ;"
LLVM,ARC,237,"LLVM_DEBUG(dbgs() << Adding store instruction:  << printReg(SrcReg, TRI) <<  to frame index  << FrameIndex << \n);"
LLVM,ARC,238,I = I + 1;
LLVM,ARC,239,std::cout << Creating InstrInfo object... << std::endl;
LLVM,ARC,240,
LLVM,ARC,241,if ( ( InstToDelete . isPHI ( ) || InstToDelete . isDebugInstr ( ) ) ) break ;
LLVM,ARC,242,}
LLVM,ARC,243,
LLVM,ARC,244,
LLVM,ARC,245,
LLVM,ARC,246,assert ( <STR_LIT> .contains ( NextReg ) && <STR_LIT> );
LLVM,ARC,247,assert ( <STR_LIT> . contains ( Instruction ) && <STR_LIT> ) ;
LLVM,ARC,248,
LLVM,ARC,249,
LLVM,ARC,250,
LLVM,ARC,251,an opening curly brace {
LLVM,ARC,252,
LLVM,ARC,253,}
LLVM,ARC,254,if (Opc >= 0x100 && Opc <= 0x1FF ) {
LLVM,ARC,255,return Opc == Instruction::Unreachable || Opc == Instruction::Br || Opc == Instruction::BrIndirect || Opc == Instruction::Switch || Opc == Instruction::IndirectBr || Opc == Instruction::Invoke || Opc == Instruction::Resume || Opc == Instruction::CatchSwitch || Opc == Instruction::CatchRet || Opc == Instruction::CleanupRet || Opc == Instruction::CatchPad || Opc == Instruction::CatchEnd;
LLVM,ARC,256,
LLVM,ARC,257,return Opcode == 8 || Opcode == 9;
LLVM,ARC,258,if (Opcode == <ISA_LIT>LOAD_FROM_STACK</ISA_LIT>) {
LLVM,ARC,259,
LLVM,ARC,260,
LLVM,ARC,261,
LLVM,ARC,262,
LLVM,ARC,263,
LLVM,ARC,264,}
LLVM,ARC,265,"`MI->addOperand(MachineOperand::CreateImm(Value), Reg, 0);"
LLVM,ARC,266,assert(MMO && Machine memory operand is valid.);
LLVM,ARC,267,return Cond [ <NUM_LIT> ] != <NUM_LIT> ;
LLVM,ARC,268,assert(MBB.contains(MachineInstr::getOpcode()));
LLVM,ARC,269,"return SelectionDAGISel(TM, OptLevel);"
LLVM,ARC,270,return: return: function body starts here
LLVM,ARC,271,return new <ISA_LIT>RegisterCoalescer (OptLevel);
LLVM,ARC,272,"return new <ISA_LIT>LegalizeDAG ( TM , OptLevel ) ;"
LLVM,ARC,273,
LLVM,ARC,274,
LLVM,ARC,275,if ( Addr . getOpcode ( ) == <STR_LIT> ) Base = Addr . getOperand ( <NUM_LIT> + 1 ) ;
LLVM,ARC,276,}
LLVM,ARC,277,
LLVM,ARC,278,
LLVM,ARC,279,
LLVM,ARC,280,
LLVM,ARC,281,"CurDAG->SelectNode(Opcode, VT, OpList, SDLoc(N));"
LLVM,ARC,282,"Tmp = CurDAG -> getNode ( Opcode , SDLoc ( N ) , SDValue ( Pred , 0 ) , SDValue ( Reg , 0 ) ) ;"
LLVM,ARC,283,"buildFrameIndex(Base->getValueType( ), FIN->getIndex( ), <STR_LIT>),<STR_LIT> );"
LLVM,ARC,284,
LLVM,ARC,285,"RegInfo . addLiveIn ( ArgRegs [ i ] , VReg ) ;"
LLVM,ARC,286,"DAG . add ( CarryOutput , <NUM_LIT> <STR_LIT> <STR_LIT> getCopyToReg ( DAG . getEntryNode ( ) , dl , FrameReg , <REG_NUM_VAL> ) ;"
LLVM,ARC,287,
LLVM,ARC,288,
LLVM,ARC,289,"return LowerGlobalTLSAddress ( Op , DAG ) ;"
LLVM,ARC,290,"SDValue V = DAG.getNode(<STR_LIT>, SDLoc(N), DAG.getVTList(<STR_LIT>, <STR_LIT>), N->getOperand(<NUM_LIT>)) ;"
LLVM,ARC,291,"setOperationAction( <STR_LIT> , <STR_LIT> , Legal ) ;"
LLVM,ARC,292,"setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ;"
LLVM,ARC,293,"setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ;"
LLVM,ARC,294,"setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ;"
LLVM,ARC,295,"bool CanLowerCall ( CallingConv :: ID CallConv , MachineFunction & MF , bool IsVarArg , const SmallVectorImpl < <STR_LIT> > & Outs, LLVMContext & Context ) const"
LLVM,ARC,296,
LLVM,ARC,297,return <STR_LIT> ;
LLVM,ARC,298,
LLVM,ARC,299,return false;
LLVM,ARC,300,
LLVM,ARC,301,"Chain = DAG.getNode(<STR_LIT>, dl, NodeTys, Ops);"
LLVM,ARC,302,default: llvm_unreachable(Unknown calling convention);
LLVM,ARC,303,
LLVM,ARC,304,MFI.setFrameAddressIsTaken(true);
LLVM,ARC,305,
LLVM,ARC,306,"SDNode *Node = DAG.getNode(ISD::GlobalAddress, dl, MVT::i64, GA) ;"
LLVM,ARC,307,
LLVM,ARC,308,"return LowerConstantPool ( Op , DAG ) ;"
LLVM,ARC,309,"Dag.getFrameIndex(FI, <STR_LIT>)."
LLVM,ARC,310,
LLVM,ARC,311,rhs = Op.getOperand(<NUM_LIT>);
LLVM,ARC,312,
LLVM,ARC,313,
LLVM,ARC,314,
LLVM,ARC,315,return false;
LLVM,ARC,316,}
LLVM,ARC,317,
LLVM,ARC,318,
LLVM,ARC,319,MF . setAlignment ( <NUM_LIT> ) ;
LLVM,ARC,320,
LLVM,ARC,321,The next statement may be an opening curly brace ({
LLVM,ARC,322,
LLVM,ARC,323,
LLVM,ARC,324,
LLVM,ARC,325,functionInfo.calculateCallStackReq();
LLVM,ARC,326,}
LLVM,ARC,327,
LLVM,ARC,328,
LLVM,ARC,329,
LLVM,ARC,330,
LLVM,ARC,331,}
LLVM,ARC,332,throw(std::runtime_error(An attempt has been made to open the output stream more than once.)) }
LLVM,ARC,333,AssemblerDirective = <STR_LIT> ;
LLVM,ARC,334,
LLVM,ARC,335,}
LLVM,ARC,336,
LLVM,ARC,337,}
LLVM,ARC,338,OutMI.setOpcode(MI->getOpcode());
LLVM,ARC,339,OutMI . addOperand ( MI -> getOperand ( 0 ) ) ;
LLVM,ARC,340,
LLVM,ARC,341,}
LLVM,ARC,342,
LLVM,ARC,343,
LLVM,ARC,344,"TargetRegistry::RegisterMCCodegenInfo(The<ISA_LIT>Target, create<ISA_LIT>MCCodeGenInfo)."
LLVM,ARC,345,throw std::runtime_error(Unable to initialize MCRegisterInfo.);
LLVM,ARC,346,MAI->setRelaxELFRelocations(true);
LLVM,ARC,347,{
LLVM,ARC,348,
LLVM,ARC,349,return MAI->getPointerSize();
LLVM,ARC,350,MAI->addInitialFrameState(Inst);
LLVM,ARC,351,}
LLVM,ARC,352,"return new ISA_LITMCInstPrinter(T, SyntaxVariant, MAI, MII, MRI);"
LLVM,ARC,353,
LLVM,ARC,354,
LLVM,ARC,355,}
LLVM,ARC,356,
LLVM,ARC,357,"TargetRegistry :: RegisterMCAsmBackend (The<ISA_LIT>Target, create<ISA_LIT>MCAsmBackend);"
LLVM,ARC,358,"TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>Target , create<ISA_LIT>MCCodeEmitter ) ;"
LLVM,ARC,359,
LLVM,ARC,360,Ldst.setDesc(AST->getInstrInfo()->get(NewOpcode));
LLVM,ARC,361,
LLVM,ARC,362,dbgs ( ) << <STR_LIT> << First;
LLVM,ARC,363,Result = nullptr;
LLVM,ARC,364,if (UsesAfterLdst.size() > UsesAfterAdd.size()) {
LLVM,ARC,365,Ldst.addOperand(MachineOperand::CreateImm(0));
LLVM,ARC,366,
LLVM,ARC,367,
LLVM,ARC,368,MF.viewCFG();
LLVM,ARC,369,
LLVM,ARC,370,dbgs() <<Fixing memory operand with a register base and a constant offset. << *First << by a single memory operation from  << *First <<  to  << *Last <<  by changing the offset operand from  << *Uses <<  to  << *Uses << \n;
LLVM,ARC,371,MachineInstr * Result = Ldst . getNextNode ( ) ;
LLVM,ARC,372,
LLVM,ARC,373,return false;
LLVM,ARC,374,
LLVM,ARC,375,return false;
LLVM,ARC,376,
LLVM,ARC,377,
LLVM,ARC,378,}
LLVM,ARC,379,}
LLVM,ARC,380,}
LLVM,ARC,381,
LLVM,ARC,382,
LLVM,ARC,383,}
LLVM,ARC,384,
LLVM,ARC,385,MO.addImm(NewOffset);
LLVM,ARC,386,MO.setImm(NewOffset);
LLVM,ARC,387,Throw an error: Void is not a recognized statement.
LLVM,ARC,388,MachineFunctionPass::run(MF) {
LLVM,ARC,389,}
LLVM,ARC,390,break;
LLVM,ARC,391,{
LLVM,ARC,392,
LLVM,ARC,393,
LLVM,ARC,394,{
LLVM,ARC,395,return false;
LLVM,ARC,396,"return noUseOfAddBeforeLoadOrStore (Add, Ldst);"
LLVM,ARC,397,
LLVM,ARC,398,
LLVM,ARC,399,<ISA_LIT>AddrMode = MF.<ISA_LIT>getAddrMode();
LLVM,ARC,400,return Changed;
LLVM,ARC,401,
LLVM,ARC,402,Offset += MF . getFrameInfo ( ) . getObjectOffset ( FrameIndex ) ;
LLVM,ARC,403,"BuildMI ( MBB , II , dl , TII . get ( MI . getOpcode ( ) ) ) . addReg ( Reg , RegState :: Define ) . addReg ( FrameReg ) . addImm ( Offset ) ;"
LLVM,ARC,404,"The next statement can vary, as the code does not include a clear conditional statement or loop. However, potential next statements could include:"
LLVM,ARC,405,
LLVM,ARC,406,
LLVM,ARC,407,assert <STR_LIT> << <STR_LIT> ;
LLVM,ARC,408,
LLVM,ARC,409,}
LLVM,ARC,410,
LLVM,ARC,411,llvm_unreachable ( ) ;
LLVM,ARC,412,"BuildMI ( MBB , II , dl , TII . get ( ADJCALLSTACKDOWNINST ) , Reg ) . addImm ( FixupImm ) . addMemOperand ( * MI . memoperands_begin ( ) ) ;"
LLVM,ARC,413,
LLVM,ARC,414,{
LLVM,ARC,415,
LLVM,ARC,416,
LLVM,ARC,417,return &MF->getTarget().getFrameLowering()->getCalleeSavedRegs(*MF);
LLVM,ARC,418,}
LLVM,ARC,419,}
LLVM,ARC,420,return TFI->hasFP(MF);
LLVM,ARC,421,Reserved.set(<STR_LIT>);
LLVM,ARC,422,
LLVM,ARC,423,
LLVM,ARC,424,}
LLVM,ARC,425,}
LLVM,ARC,426,
LLVM,ARC,427,}
LLVM,ARC,428,
LLVM,ARC,429,
LLVM,ARC,430,
LLVM,ARC,431,
LLVM,ARC,432,return;
LLVM,ARC,433,
LLVM,ARC,434,
LLVM,ARC,435,
LLVM,ARC,436,return FrameLowering;
LLVM,ARC,437,if ( VR.WidgetBar ) {
LLVM,ARC,438,}
LLVM,ARC,439,}
LLVM,ARC,440,return targetLowering;
LLVM,ARC,441,
LLVM,ARC,442,}
LLVM,ARC,443,"RegisterTarget < Triple :: abc > Y ( getThe<ISA_LIT>Target ( ) , <STR_LIT> , <STR_LIT> ) ;"
LLVM,ARC,444,}
LLVM,ARC,445,
LLVM,ARC,446,
LLVM,ARC,447,<TAB>}
LLVM,ARC,448,TLOF = TargetLoweringObjectFileELF() ;
LLVM,ARC,449,return an optional CodeModel::Model object named effectiveCodeModel.
LLVM,ARC,450,
LLVM,ARC,451,if ( MArch) {
LLVM,ARC,452,"return TargetTransformInfo( <ISA_LIT>TTIImpl(this, F) );"
LLVM,ARC,453,return true;
LLVM,ARC,454,
LLVM,ARC,455,
LLVM,ARC,456,TargetPassConfig::initialize();
LLVM,ARC,457,
LLVM,ARC,458,}
LLVM,ARC,459,
LLVM,ARC,460,PASS_DEVICE_ANALYSIS }
LLVM,ARC,461,
LLVM,ARC,462,}
LLVM,ARC,463,}
LLVM,ARC,464,
LLVM,ARC,465,
LLVM,ARC,466,getThe<ISA_LIT>Target();
LLVM,ARC,467,}
LLVM,ARC,468,Closing bracket (}
LLVM,ARC,469,
LLVM,ARC,470,
LLVM,ARC,471,
GCC,riscv,1009,rtx bases[2];
LLVM,NVPTX,646,if (MF.hasPseudoInstr()) {
LLVM,RISCV,2836,
LLVM,ARC,205,Closing curly brace }
LLVM,NVPTX,1504,return Flt.convertToFloat();